Abstract: A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers on opposite sides of the first channel layer; forming second source/drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. Multiple fins are formed extending from the substrate, the fins including a first group of active fins in an active region and an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions, the inactive fin separated from its closest active fin by a second trench region, and the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

Abstract: An expansion card frame assembly is configured to support a riser card and an expansion card. The expansion card frame assembly includes a frame, a pivotable component and a stopper. The frame is configured to support the riser card, and the expansion card is configured to be inserted into the riser card. The pivotable component is pivotably disposed on the frame and configured to be located aside the expansion card. The stopper is movably disposed on the pivotable component and configured to be located at one side of the expansion card which is located farther away from the riser card.

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Abstract: A circuit includes a level shifter circuit, an output circuit, and a first feedback circuit. The level shifter circuit is coupled to a first voltage supply, and configured to receive an enable signal, a first input signal or a second input signal, and to generate a first and second signal responsive to the enable signal or the first input signal. The output circuit coupled to the level shifter circuit and the first voltage supply, and configured to generate an output signal or a first feedback signal responsive to the first signal, and configured to latch a previous state of the output signal in response to the enable signal or an inverted enable signal. The first feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and configured to receive at least the enable signal, the inverted enable signal or the first feedback signal.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, and a polymer over the die and the molding. The die has a top surface. The molding has a top surface. The polymer has a first bottom surface contact the die and a second surface contacting the molding. The first bottom surface is at a level substantially same as the second bottom surface.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: An electronic device and a power management method thereof are provided. The power management method includes: detecting a plurality of status information of a plurality of operation statuses of a battery set; determining an information value range within which each of the status information of each of the operation statuses falls, calculating a weighting value of each of the operation statuses according to the information value range; and calculating a weighting value sum corresponding to the weighting values of the operation statuses to set a load capacity of the battery set according to the weighting value sum.

Abstract: An expanded spinal fusion cage is provided and includes: an outer frame; a sliding block set with a middle sliding block located within the outer frame, and the middle sliding block is located between two outer sliding blocks; a screw rod penetrating through and combined with the outer frame, and the screw rod is screwed with the middle sliding block, so that the middle sliding block is moved in translation in the outer frame and simultaneously expands the two outer sliding blocks by rotating the screw rod; two curved surface elements located outside the outer frame and combined with the two outer sliding blocks respectively, each of the curved surface elements has a wing plate; and two vertebral arch screws penetrating through and combined with the two wing plates.

Abstract: Disclosed herein is a method of treating a tumor in a subject. The method comprises administering to the subject a molecular construct, which comprises an anti-CD38 antibody, and a plurality of lenalidomide molecules or hydrolyzed lenalidomide molecules linked to the anti-CD38 antibody. According to some embodiments of the present disclosure, the administration of the molecular construct gives rise to an effective amount of the lenalidomide molecules or the hydrolyzed lenalidomide molecules that is at least 1,000 times less than an effective amount of the lenalidomide molecule used alone or in combination with the anti-CD38 antibody for the treatment of the tumor.

Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

Abstract: A fan system and a computing system with the fan system are disclosed. The fan system includes a fan module. The fan module includes a housing configured to retain a fan and a motor to rotate the fan. The housing includes an air inlet aperture on an air inlet side of the housing and an air outlet aperture on an air outlet side of the housing. The fan system further includes an outlet fan guard coupled to the fan module on the air outlet side of the housing. The outlet fan guard includes at least one flap rotatable between a closed position, covering the air outlet aperture of the housing, and an open position, uncovering the air outlet aperture of the housing. The outlet fan guard further includes at least one spring urging the at least one flap into the closed position.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.