Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: A carrier for different form factors for insertion in a slot of a computing device is disclosed. The different form factors have different thicknesses defined by the E1.S specification. The carrier includes a base holding a first type of form factor. A bezel is configurable for insertion in a slot for a device of the first type of form factor. The bezel has an attachment surface. The base is attachable to the attachment surface of the bezel. A second type of form factor is also attachable to the attachment surface of the bezel. A cover encloses the first type of form factor when joined to the base. The base and cover are discarded when the second type of form factor is attached to the bezel. The attached bezel and second type of form factor may also be inserted in the slot.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A LCD panel includes a gate driver, an active-matrix array and a switching circuit. The gate driver is disposed on a thin film transistor substrate, and includes a shift register, wherein the shift register has plural output terminals for successively outputting plural gate driving signals. The active-matrix array is disposed on the thin film transistor substrate, and includes plural gate lines, wherein the gate lines are connected with the output terminals of the shift register. The switching circuit is disposed on the thin film transistor substrate, and includes plural switching units, wherein each of the switching units has a first terminal electrically connected with one of the output terminals of the shift register, a control terminal electrically connected with a first input pad, and a second terminal electrically connected with a second input pad.

Abstract: A LCD panel includes a gate driver, an active-matrix array and a switching circuit. The gate driver is disposed on a thin film transistor substrate, and includes a shift register, wherein the shift register has plural output terminals for successively outputting plural gate driving signals. The active-matrix array is disposed on the thin film transistor substrate, and includes plural gate lines, wherein the gate lines are connected with the output terminals of the shift register. The switching circuit is disposed on the thin film transistor substrate, and includes plural switching units, wherein each of the switching units has a first terminal electrically connected with one of the output terminals of the shift register, a control terminal electrically connected with a first input pad, and a second terminal electrically connected with a second input pad.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes a pull-up unit, an input unit for receiving an input signal, an energy-store unit for providing a driving control voltage in response to the input signal, a discharging unit, a couple unit and a pull-down unit. The pull-up unit pulls up a first gate signal in response to the driving control voltage. The discharging unit performs a discharging operation for pulling down the driving control voltage. The couple unit is utilized for coupling the energy-store unit with a succeeding shift register circuit stage so that the falling edge of a second gate signal generated by the succeeding shift register stage is capable of shifting down the driving control voltage. The pull-down unit pulls down the first gate signal in response to the second gate signal.