Abstract: A voltage regulator with diode retention is shown, which includes an input terminal receiving a supply voltage, an output terminal providing a regulated voltage, and a main circuit coupled between the input terminal and the output terminal. In a normal mode, the main circuit transforms the supply voltage to a first voltage as the regulated voltage. In a sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator, to generate a second voltage as the regulated voltage. The second voltage is lower than the first voltage.

Abstract: A multi-level digital step attenuator (DSA) with a hybrid attenuation circuit is shown. The hybrid attenuation circuit is coupled between an input node and an output node of the multi-level DSA. The bypass switch of the multi-level DSA is controlled to provide a bypass path between the input node and the output node of the of the multi-level DSA when the hybrid attenuation circuit is in a disabled state. In the first active state, the hybrid attenuation circuit is switched to form a T-type structure to provide a first amount of signal attenuation. In the second active state, the hybrid attenuation circuit is switched to form a Pi-type structure to provide a second amount of signal attenuation.

Abstract: A digital step attenuator (DSA) with efficient high-frequency signal attenuation is shown. The DSA has an attenuation circuit, a bypass switch, and a diversion circuit. The attenuation circuit is coupled between an input node and an output node of the digital step attenuator. The bypass switch is controlled by a bypass control signal to provide a bypass path between the input node and the output node of the digital step attenuator. The diversion circuit couples a control terminal of the bypass switch to a ground terminal in response to the bypass control signal being in an inactive state.

Abstract: A method for designing an integrated circuit layout includes: generating an analog standard cell library and designing the integrated circuit layout by using at least the analog standard cell library, where the step of generating the analog standard cell library includes creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells. Another method for designing an integrated circuit layout includes: generating a mixed-signal standard cell library and designing the integrated circuit layout by using at least the mixed-signal standard cell library, where the step of generating the mixed-signal standard cell library includes creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.

Abstract: A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

Abstract: A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

Abstract: The present invention discloses a DAC device including a positive DAC, a negative DAC and an output circuit. The positive DAC is configured to perform a digital-to-analog converting operation on a digital input signal based on a first pulse signal to generate a first analog signal, wherein the first analog signal comprises a convolution result of the first pulse signal and the digital input signal. The negative DAC is configured to perform the digital-to-analog converting operation on the digital input signal based on a second pulse signal to generate a second analog signal, wherein the second analog signal comprises a convolution result of the second pulse signal and the digital input signal. The output circuit is configured to generate an output analog signal according to the first analog signal and the second analog signal.

Abstract: A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.

Abstract: In a computing device for identifying cosmetic products and simulating application of the cosmetic products, a target image is obtained from a user, where the target image depicts at least one of a cosmetic product or an individual wearing at least one cosmetic product. The computing device accesses a database storing a plurality of sample images, each sample image having a corresponding image feature map and metadata. The computing device analyzes the target image and identifies a matching sample image among the plurality of sample images based on the image feature map. The computing device obtains an image or video with a facial region of the user via a camera and generates a user interface displaying a resulting image or video showing virtual application of the at least one cosmetic product on the user. The computing device also displays cosmetic product information to the user in the user interface.

Abstract: Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

Abstract: Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k?1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k?1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k?1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k?1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Abstract: Various embodiments are disclosed for selecting a region of interest within an object. One embodiment is a method for editing a digital image in an image editing device. The method comprises obtaining a first position within a digital image, the first position being specified by a pointer. The method further comprises defining a first selection region based on the first position and obtaining a second position within the digital image, the second position being specified by the pointer. The method further comprises determining movement of the pointer between the first position and the second position and predicting future movement by the pointer based on the determined movement. Based on the determined movement and the predicted future movement, the first selection region is expanded to define a second selection region.

Abstract: A digital-to-analog converter apparatus includes a digital-to-analog converter, a resistor-capacitor circuit, a quantizer and a controller. The resistor-capacitor circuit includes an operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a first switch and a second switch. The digital-to-analog converter may generate a plurality of currents. The quantizer may generate a plurality of offset values. The controller may control coupling of the plurality of currents to the operational amplifier.

Abstract: Various embodiments are disclosed for selecting a region of interest within an object. One embodiment is a method for editing a digital image in an image editing device. The method comprises obtaining a first position within a digital image, the first position being specified by a pointer. The method further comprises defining a first selection region based on the first position and obtaining a second position within the digital image, the second position being specified by the pointer. The method further comprises determining movement of the pointer between the first position and the second position and predicting future movement by the pointer based on the determined movement. Based on the determined movement and the predicted future movement, the first selection region is expanded to define a second selection region.