Patents by Inventor Wei-Hsiu Hsu
Wei-Hsiu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916075Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.Type: GrantFiled: May 10, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
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Patent number: 11837552Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: May 19, 2022Date of Patent: December 5, 2023Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Patent number: 11695439Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.Type: GrantFiled: October 19, 2021Date of Patent: July 4, 2023Assignee: MEDIATEK INC.Inventors: Jui-Lin Hsu, Yen-Tso Chen, Hsiang-Yun Chu, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
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Patent number: 11677433Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.Type: GrantFiled: October 4, 2018Date of Patent: June 13, 2023Assignee: MediaTek Inc.Inventors: Jui-Lin Hsu, Chao-Ching Hung, Tzu-Chin Lin, Wei-Hsiu Hsu, Yu-Li Hsueh, Jing-Hong Conan Zhan, Chih-Ming Hung
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Publication number: 20230179240Abstract: A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Applicant: MEDIATEK INC.Inventors: Jui-Lin Hsu, Hsiang-Yun Chu, Yen-Tso Chen, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
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Patent number: 11601147Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.Type: GrantFiled: October 18, 2021Date of Patent: March 7, 2023Assignee: MEDIATEK INC.Inventors: Jui-Lin Hsu, Hsiang-Yun Chu, Yen-Tso Chen, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
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Publication number: 20220352084Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: ApplicationFiled: May 19, 2022Publication date: November 3, 2022Applicant: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Patent number: 11373957Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: August 17, 2020Date of Patent: June 28, 2022Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Publication number: 20220140849Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.Type: ApplicationFiled: October 19, 2021Publication date: May 5, 2022Applicant: MEDIATEK INC.Inventors: Jui-Lin Hsu, Yen-Tso Chen, Hsiang-Yun Chu, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
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Publication number: 20220140848Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.Type: ApplicationFiled: October 18, 2021Publication date: May 5, 2022Applicant: MEDIATEK INC.Inventors: Jui-Lin Hsu, Hsiang-Yun Chu, Yen-Tso Chen, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
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Publication number: 20200381365Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
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Patent number: 10784206Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: October 18, 2018Date of Patent: September 22, 2020Assignee: MEDIATEK INC.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Publication number: 20190207640Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.Type: ApplicationFiled: October 4, 2018Publication date: July 4, 2019Inventors: Jui-Lin Hsu, Chao-Ching Hung, Tzu-Chin Lin, Wei-Hsiu Hsu, Yu-Li Hsueh, Jing-Hong Conan Zhan, Chih-Ming Hung
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Publication number: 20190051609Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.Type: ApplicationFiled: October 18, 2018Publication date: February 14, 2019Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
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Patent number: 9496444Abstract: The invention is related to a method for forming dendritic silver with periodic structure as light-trapping layer, includes these steps: form a photoresist layer on a conductive substrate, and at least two coherent light beams is provided in using a laser interference lithography apparatus, to form a plurality of particular patterns respectively on the setting-exposure positions of the conductive substrate in sequence till the particular periods pattern formed. Thereafter, form the dendritic silver nanostructure with period pattern on the conductive substrate via electrochemical process, wherein operating voltage is 2V or higher, and electrochemical reaction time is 10 sec or higher.Type: GrantFiled: February 3, 2015Date of Patent: November 15, 2016Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUANInventors: Der-Jun Jan, Shih-Shou Lo, Wei-Hsun Lai, Wei-Hsiu Hsu
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Publication number: 20160099364Abstract: The invention is related to a method for forming dendritic silver with periodic structure as light-trapping layer, includes these steps: form a photoresist layer on a conductive substrate, and at least two coherent light beams is provided in using a laser interference lithography apparatus, to form a plurality of particular patterns respectively on the setting-exposure positions of the conductive substrate in sequence till the particular periods pattern formed. Thereafter, form the dendritic silver nanostructure with period pattern on the conductive substrate via electrochemical process, wherein operating voltage is 2V or higher, and electrochemical reaction time is 10 sec or higher.Type: ApplicationFiled: February 3, 2015Publication date: April 7, 2016Inventors: DER-JUN JAN, SHIH-SHOU LO, WEI-HSUN LAI, WEI-HSIU HSU
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Patent number: 8274320Abstract: A signal processing circuit includes a differential input circuit, a first DC filter, a second DC filter, a differential transconductance circuit, and a differential converting circuit. The differential input circuit includes first and second input circuits respectively for receiving first and second input signals to generate first and second processed signals. The first DC filter and the second DC filter, respectively coupled to the first and the second input circuits, receive the first and the second processed signals and output first and second voltage signals. The differential transconductance circuit includes first and second transconductance circuits, respectively coupled to the first and the second DC filters, for converting the first and the second voltage signals to first and second current signals.Type: GrantFiled: July 19, 2010Date of Patent: September 25, 2012Assignee: MStar Semiconductor, Inc.Inventors: Wei-Hsiu Hsu, Shuo Yuan Hsiao
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Publication number: 20110025417Abstract: A signal processing circuit includes a differential input circuit, a first DC filter, a second DC filter, a differential transconductance circuit, and a differential converting circuit. The differential input circuit includes first and second input circuits respectively for receiving first and second input signals to generate first and second processed signals. The first DC filter and the second DC filter, respectively coupled to the first and the second input circuits, receive the first and the second processed signals and output first and second voltage signals. The differential transconductance circuit includes first and second transconductance circuits, respectively coupled to the first and the second DC filters, for converting the first and the second voltage signals to first and second current signals.Type: ApplicationFiled: July 19, 2010Publication date: February 3, 2011Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Wei-Hsiu Hsu, Shuo Yuan Hsiao
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Patent number: D570800Type: GrantFiled: November 27, 2006Date of Patent: June 10, 2008Assignee: Uniband Electronic Corp.Inventors: Hui-Mei Chen, Wei-Hsiu Hsu, Huan-Ping Su, Chien-Hsin Su