Patents by Inventor Wei-Hsiung Tseng

Wei-Hsiung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132001
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Publication number: 20240244007
    Abstract: A reordering method performed by a receiving apparatus is provided. The receiving apparatus may receive a first PPDU from a transmitting apparatus, wherein the first PPDU includes a plurality of MPDUs, and the MPDUs correspond to the same BA window. The receiving apparatus may determine a traffic that each of the MPDUs belongs to according to an MPDU identification, wherein traffics that the plurality of MPDUs belonging to include a first traffic and a second traffic which is different from the first traffic. The receiving apparatus may perform a reordering operation for the MPDUs belonging to the first traffic, and a reordering operation for the MPDUs belonging to the second traffic, respectively. The receiving apparatus may transmit a BA frame in response to the first PPDU to the transmitting apparatus, wherein the BA frame includes information for indicating whether the MPDUs in the first PPDU have been successfully received.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Chi-Han HUANG, Yen-Hsiung TSENG, Cheng-Ying WU, Wei-Wen LIN
  • Publication number: 20240030140
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: YONG KONG SIEW, WEI HSIUNG TSENG, CHANGHWA KIM
  • Patent number: 11804438
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Publication number: 20220199534
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: YONG KONG SIEW, WEI HSIUNG TSENG, CHANGHWA KIM
  • Patent number: 11335637
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region with an etch stop layer interposed therebetween, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Publication number: 20190333856
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer, and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first inter layer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second inter layer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Inventors: YONG KONG SIEW, WEI HSIUNG TSENG, CHANGHWA KIM
  • Patent number: 10396034
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Publication number: 20180096934
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Application
    Filed: April 21, 2017
    Publication date: April 5, 2018
    Inventors: YONG KONG SIEW, WEI HSIUNG TSENG, CHANGHWA KIM
  • Patent number: 9553094
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Publication number: 20160315087
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: March 14, 2016
    Publication date: October 27, 2016
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Patent number: 9287181
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Patent number: 9240484
    Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: January 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9166010
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Publication number: 20150270177
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: January 8, 2015
    Publication date: September 24, 2015
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Publication number: 20150243745
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Publication number: 20150236160
    Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9054213
    Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Yasutoshi Okuno, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: RE48942
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng