Patents by Inventor WEI-HSUAN LIN

WEI-HSUAN LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Patent number: 11977251
    Abstract: A backlight module including a light guide plate, a light source, an upper prism sheet, and a lower prism sheet is provided. The light guide plate has a light incident surface and a light emitting surface. The upper prism sheet is disposed at a side of the light emitting surface of the light guide plate. The upper prism sheet includes an upper substrate and first prism microstructures. Cross-sections of the first prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 80 to 90 degrees. The lower prism sheet is disposed between the light guide plate and the upper prism sheet. The lower prism sheet includes a lower substrate and second prism microstructures. Cross-sections of the second prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 100 to 130 degrees.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 7, 2024
    Assignee: Coretronic Corporation
    Inventors: Chun-Hsiang Hsu, Yen-Hao Lin, Wei-Hsuan Cheng
  • Patent number: 11976374
    Abstract: A method and device of removing and recycling metals from a mixing acid solution, includes adsorbing a mixing acid solution with a pH value of ?1 to 4 and a cobalt ion concentration of 100 to 1,000 mg/L by at least two cation resins in series setting to the cobalt ion concentration in the mixing acid solution is less than 10 mg/L, and then adjusting the pH value of the mixing acid solution after adsorption to meet a discharge standard, wherein the particle size of the at least two cation resins in series setting is 150˜1,200 ?m. After the cation resins are saturated by adsorption, regenerating the cation resins by sulfuric acid to form a cobalt sulfate solution, and then electrolytically treating the cobalt sulfate solution to obtain electrolytic cobalt and sulfuric acid electrolyte. The operation process is simple without complicated equipment, and it can effectively recycle metals from mixing acid solutions.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 7, 2024
    Assignee: MEGA UNION TECHNOLOGY INCORPORATED
    Inventors: Kuo-Ching Lin, Yung-Cheng Chiang, Shr-Han Shiu, Wei-Rong Tey, Yu-Hsuan Li
  • Publication number: 20240145650
    Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240113202
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Publication number: 20240102934
    Abstract: A test strip detecting system includes a test strip, a test strip detecting carrier and a mobile communication apparatus. The test strip detecting carrier includes a container structure, positioning markers and colorimetric calibrating blocks, and the colorimetric calibrating blocks are embedded inside the positioning markers. The test strip is placed in the container structure and reacts with a specimen to generate color blocks. The mobile communication apparatus controls an image capture unit to capture an original image of the test strip placed in the test strip detecting carrier; detects the positioning markers in the original image to obtain a plurality of coordinates of the positioning markers; performs image coordinate calibration according to the plurality of coordinates to generate a calibrated image; and performs a colorimetric calibration for the color blocks and the colorimetric calibrating blocks according to the calibrated image so as to generate a test result.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 28, 2024
    Applicant: National Cheng Kung University
    Inventors: Yu-Cheng Lin, Wei-Chien Weng, Yi-Hsuan Chen
  • Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Patent number: 11934065
    Abstract: A display device includes a substrate, a first light emitting element, a second light emitting element, and an optical film sheet. The first light emitting element and the second light emitting element are disposed on the substrate. The first light emitting element emits a first light, and the first light has a first wavelength range. The second light emitting element emits a second light, and the second light has a second wavelength range. The optical film sheet is disposed above the first light emitting element and the second light emitting element. The optical film sheet includes a first zone and a second zone. The first zone includes a first cholesteric liquid crystal, and the first cholesteric liquid crystal reflects light in at least the first wavelength range. The second zone includes a second cholesteric liquid crystal, and the second cholesteric liquid crystal reflects light in at least the second wavelength range.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: March 19, 2024
    Assignee: AUO Corporation
    Inventors: Wan Heng Chang, Min-Hsuan Chiu, Syuan-Ying Lin, Wei-Ming Cheng
  • Publication number: 20240030821
    Abstract: A novel power supply apparatus (10) includes a microcontroller (102) and a plurality of voltage converters (104). If the voltage converters (104) are in a boost mode and a plurality of duty cycles of the voltage converters (104) calculated by the microcontroller (102) are less than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5. If the voltage converters (104) are in a buck mode and the duty cycles of the voltage converters (104) calculated by the microcontroller (102) are greater than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Lien-Hsing CHEN, Ta-Wen CHANG, Hsiao-Hua CHI, Ching-Ming LAI, Wei-Hsuan LIN
  • Patent number: 11866838
    Abstract: A method for creating colorful patterns on a metal surface by using colorless ink is revealed. First carry out a first anodizing process on a metal substrate to form a first anodic oxide layer on a surface of the metal substrate. Then coat a layer of colorless ink on the first anodic oxide layer on the surface of the metal substrate to form a colorless ink pattern mask. Later perform a second anodizing process to form a second anodic oxide layer on a part of the metal substrate without being covered with the colorless ink pattern mask. Next remove the colorless ink pattern mask and coat a metal film over the first anodic oxide layer and the second anodic oxide layer to get a colorful pattern on the metal substrate.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 9, 2024
    Assignee: National Cheng Kung University
    Inventors: Chen-Kuei Chung, Chin-Jou Kuo, Wei-Hsuan Lin
  • Publication number: 20220372645
    Abstract: A method for creating colorful patterns on a metal surface by using colorless ink is revealed. First carry out a first anodizing process on a metal substrate to form a first anodic oxide layer on a surface of the metal substrate. Then coat a layer of colorless ink on the first anodic oxide layer on the surface of the metal substrate to form a colorless ink pattern mask. Later perform a second anodizing process to form a second anodic oxide layer on a part of the metal substrate without being covered with the colorless ink pattern mask. Next remove the colorless ink pattern mask and coat a metal film over the first anodic oxide layer and the second anodic oxide layer to get a colorful pattern on the metal substrate.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: CHEN-KUEI CHUNG, CHIN-JOU KUO, WEI-HSUAN LIN