Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.

Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.

Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.

Abstract: A manufacture method of a multilayer structure having a non-polar a-plane {11-22} III-nitride layer includes forming a nucleation layer on a r-plane substrate, wherein the nucleation layer is composed of multiple nitride layers; and forming a non-polar a-plane {11-20} III-nitride layer on the nucleation layer. The nucleation layer features reduced stress, reduced phase difference of lattice, blocked elongation of dislocation, and reduced density of dislocation. Thus, the non-polar a-plane {11-20} III-nitride layer with flat surface can be formed.

Abstract: The invention discloses etching method for the nitride semiconductor. Firstly dielectric layer is formed on gallium nitride. The line pattern or dot pattern is formed on the dielectric layer by using the exposure, development, and etching processes. The dielectric layer is used as the mask for the epitaxial lateral overgrowth of follow-up gallium nitride layer. The thick gallium nitride film is grown on the dielectric layer. Then the wet etching process is used to remove the dielectric layer, and the thick gallium nitride film on the dielectric layer is etched to form the specific shape as required.

Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.

Abstract: A manufacture method of a multilayer structure having a non-polar a-plane {11-22} III-nitride layer includes forming a nucleation layer on a r-plane substrate, wherein the nucleation layer is composed of multiple nitride layers; and forming a non-polar a-plane {11-20} III-nitride layer on the nucleation layer. The nucleation layer features reduced stress, reduced phase difference of lattice, blocked elongation of dislocation, and reduced density of dislocation. Thus, the non-polar a-plane {11-20} III-nitride layer with flat surface can be formed.

Abstract: The invention discloses etching method for the nitride semiconductor. Firstly dielectric layer is formed on gallium nitride. The line pattern or dot pattern is formed on the dielectric layer by using the exposure, development, and etching processes. The dielectric layer is used as the mask for the epitaxial lateral overgrowth of follow-up gallium nitride layer. The thick gallium nitride film is grown on the dielectric layer. Then the wet etching process is used to remove the dielectric layer, and the thick gallium nitride film on the dielectric layer is etched to form the specific shape as required.

Abstract: An AF assistance apparatus comprises a lamp, a shading sheet and a control unit. The control unit, coupled to the lamp, turns on the lamp to emit light or signals through the shading sheet after receiving an enabling signal, and turns off the lamp after receiving a disabling signal.