Patents by Inventor Wei-I Li

Wei-I Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847634
    Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-En Cheng, Chun-Te Li, Kai-Hsuan Lee, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20200365454
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, and depositing a first dielectric material on the first semiconductor fin and the second semiconductor fin on the semiconductor substrate using an atomic layer deposition process. There is a first trench between the first semiconductor fin and the second semiconductor fin. The method also includes filling the first trench with a flowable dielectric material, and heating the flowable dielectric material and the first dielectric material to form an isolation structure between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi KAO, Wei-Jin LI, Chung-Chi KO, Yu-Cheng SHIAU, Han-Sheng WENG, Chih-Tang PENG, Tien-I BAO
  • Patent number: 10743926
    Abstract: An osteo-implant including two end portions, at least one middle structure, and a plurality of connection portions is provided. The middle structure is disposed between the two end portions and includes a plurality of middle portions. The middle portions are connected to the two end portions through the connection portions. When the two end portions are moved relatively along an axial direction of the osteo-implant, the two end portions drive the middle portions to push with each other and have displacements along a radial direction of the osteo-implant through the connection portions, such that an outer diameter of the osteo-implant is increased by the middle portions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Jun Li, Hong-Jen Lai, Pei-I Tsai, Fang-Hei Tsau, Wei-Chin Huang, Yu-Tsung Chiu
  • Publication number: 20200197059
    Abstract: An osteo-implant including two end portions, at least one middle structure, and a plurality of connection portions is provided. The middle structure is disposed between the two end portions and includes a plurality of middle portions. The middle portions are connected to the two end portions through the connection portions. When the two end portions are moved relatively along an axial direction of the osteo-implant, the two end portions drive the middle portions to push with each other and have displacements along a radial direction of the osteo-implant through the connection portions, such that an outer diameter of the osteo-implant is increased by the middle portions.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Jun Li, Hong-Jen Lai, Pei-I Tsai, Fang-Hei Tsau, Wei-Chin Huang, Yu-Tsung Chiu
  • Patent number: 10586895
    Abstract: A LED chip including a first semiconductor layer; an active layer; a second semiconductor layer; a plurality of indentations, wherein each indentation extends downward to reach and expose the first semiconductor layer, wherein each indentation includes a bottom part and two side surfaces in a cross sectional view; an exposing area exposing the first semiconductor layer at a side of the LED chip; a first metal layer disposed on the second semiconductor layer and electrically connecting to the first semiconductor layer; and a first insulating layer formed between the first metal layer and the second semiconductor layer to isolate the first metal layer from the second semiconductor layer; wherein the first metal layer continuously extends to the plurality of indentations, covers the bottom part, the two side surfaces of each indentation and a top surface of the second semiconductor layer around the two side surfaces and contacts the exposing area; and wherein the first metal layer includes a plurality of recesse
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 10, 2020
    Assignee: Epistar Corporation
    Inventors: Han-Zhong Liao, Chih-Hsuan Lu, Fang-I Li, Wei-Kang Cheng, Shyi-Ming Pan
  • Patent number: 10396040
    Abstract: An electronic package is provided, which includes: a carrier; a plurality of electronic elements disposed on the carrier; a bather frame disposed on the carrier and positioned between adjacent two of the electronic elements; an encapsulant formed on the carrier and encapsulating the electronic elements and the bather frame with a portion of the bather frame protruding from the encapsulant; and a shielding element disposed on the encapsulant and being in contact with the portion of the bather frame protruding from the encapsulant. Therefore, the electronic package has an electromagnetic interference (EMI) shielding effect improved. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yue-Ying Jian, Wei-Ping Wang, Tsung-Ming Li, En-Li Lin, Kaun-I Cheng, Yu-De Chu
  • Patent number: 10374038
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
  • Publication number: 20190207061
    Abstract: A LED chip including a first semiconductor layer; an active layer; a second semiconductor layer; a plurality of indentations, wherein each indentation extends downward to reach and expose the first semiconductor layer, wherein each indentation includes a bottom part and two side surfaces in a cross sectional view; an exposing area exposing the first semiconductor layer at a side of the LED chip; a first metal layer disposed on the second semiconductor layer and electrically connecting to the first semiconductor layer; and a first insulating layer formed between the first metal layer and the second semiconductor layer to isolate the first metal layer from the second semiconductor layer; wherein the first metal layer continuously extends to the plurality of indentations, covers the bottom part, the two side surfaces of each indentation and a top surface of the second semiconductor layer around the two side surfaces and contacts the exposing area; and wherein the first metal layer includes a plurality of recesse
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Inventors: Han-Zhong Liao, Chih-Hsuan Lu, Fang-I Li, Wei-Kang Cheng, Shyi-Ming Pan
  • Publication number: 20190165100
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Application
    Filed: March 15, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I KUO, Chii-Horng LI, Chia-Ling CHAN, Li-Li SU, Yi-Fang PAI, Wei Te CHIANG, Shao-Fu FU, Wei Hao LU
  • Patent number: 8653795
    Abstract: The present invention discloses a charger circuit. The charger circuit comprises a control circuit and at least two charging paths. The control circuit determines to activate or inactivate each charging path according to a battery feedback signal representing the charging status. Accordingly, the battery is charged by input power in an optimal way so that the charging efficiency is improved and the overheating problem is solved.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: February 18, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Hsuan-Kai Wang, Nien-Hui Kung, Wei-I Li
  • Publication number: 20120112705
    Abstract: The present invention discloses a charger circuit. The charger circuit comprises a control circuit and at least two charging paths. The control circuit determines to activate or inactivate each charging path according to a battery feedback signal representing the charging status. Accordingly, the battery is charged by input power in an optimal way so that the charging efficiency is improved and the overheating problem is solved.
    Type: Application
    Filed: May 26, 2011
    Publication date: May 10, 2012
    Inventors: Hsuan-Kai Wang, Nien-Hui Kung, Wei-I Li