Patents by Inventor Wei-Je (Robert) Huang

Wei-Je (Robert) Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10275275
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 30, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Patent number: 10180916
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20170161100
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20170161099
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20080104378
    Abstract: System configuration data is transferred from a master integrated circuit to a shadow integrated circuit in a computer system before the system is initialized. The configuration data is initially stored in configuration registers in the master integrated circuit. The configuration data may include values that are programmed via hardware (e.g., strapped pin values) or software (e.g., default or overridden values). A CPU accesses the configuration data in the configuration registers through a host module of the shadow integrated circuit. A copy of the configuration data is transferred to shadow registers in the shadow integrated circuit. After system initialization, the CPU may execute software to read configuration values directly from the configuration registers on the master integrated circuit. The CPU may also execute a write operation on the configuration data in both the configuration registers and the shadow registers such that the configuration settings are consistent across the system.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 1, 2008
    Applicant: NVIDIA Corporation
    Inventors: Wei-Je (Robert) Huang, Bruce R. Intihar, Prakash G. Apte, Thomas H. Teng