Patents by Inventor Wei Jern Tan

Wei Jern Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Rod-based substrate with ringed interconnect layers
    Patent number: 11239126
    Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Florence Su Sin Phun, Wei Jern Tan, Boon Ping Koh, Nik Mohamed Azeim Nik Zurin, Kai Chong Ng
  • ROD-BASED SUBSTRATE WITH RINGED INTERCONNECT LAYERS
    Publication number: 20210074598
    Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.
    Type: Application
    Filed: March 31, 2017
    Publication date: March 11, 2021
    Inventors: Florence Su Sin Phun, Wei Jern Tan, Boon Ping Koh, Nik Mohamed Azeim Nik Zurin, Kai Chong Ng
  • PRINTED CIRCUIT BOARD USING TWO-VIA GEOMETRY
    Publication number: 20200187352
    Abstract: To reduce the effect of undesirable electrical resonances in via stubs (e.g., portions of electrically conductive material in a via that form an open circuit by electrically connecting at only one end), a multi-layer printed circuit board can electrically connect traces in different layers using two vias that are electrically connected to each other. For example, a first electrical trace can electrically connect to a first via at a first layer, the first via can electrically connect to a second via at the topmost layer (or the bottommost layer), and the second via can electrically connect to a second electrical trace at a second layer. Compared to a typical single-via connection scheme, the two-via connection scheme can produce stubs that are shorter in length and therefore have an increased resonant frequency that may avoid interference with electrical signals sent through the first and second electrical traces.
    Type: Application
    Filed: October 24, 2019
    Publication date: June 11, 2020
    Inventors: Wei Jern Tan, Tony Lewis
  • IMPEDANCE MATCHING IN A TRANSMISSION LINE
    Publication number: 20160173055
    Abstract: Techniques for impedance matching are described herein. The techniques include an apparatus for impedance matching including a trace section having a load impedance. The trace section comprises characteristics generating an impedance match between a main channel impedance and the load impedance.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Applicant: INTEL CORPORATION
    Inventors: Michael W. Leddige, Wei Jern Tan, Chee Kit Chew, Natasya Athirah Abdul Khalid, Howard L. Heck