Patents by Inventor Wei-Jhih Hsieh

Wei-Jhih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for improving accuracy of parasitics extraction considering sub-wavelength lithography effects
    Patent number: 8438505
    Abstract: The present disclosure involves a method. The method includes decomposing a layout of a circuit into a plurality of patterns. The method includes generating a plurality of contours to represent the plurality of patterns after the patterns have been subjected to a manufacturing process. The method includes generating a plurality of polygons that approximate geometries of the contours, respectively. The method includes associating each of the polygons with a respective one of a plurality of pattern elements in a pattern library, wherein the pattern elements each include a shape that resembles the associated polygon and electrical parameters extracted from the shape. The method includes calculating electrical performance of the circuit based on the pattern elements associated with the polygons.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Kuen-Yu Tsai, Wei-Jhih Hsieh, Bo-Sen Chang
  • METHOD FOR IMPROVING ACCURACY OF PARASITICS EXTRACTION CONSIDERING SUB-WAVELENGTH LITHOGRAPHY EFFECTS
    Publication number: 20120185807
    Abstract: The present disclosure involves a method. The method includes decomposing a layout of a circuit into a plurality of patterns. The method includes generating a plurality of contours to represent the plurality of patterns after the patterns have been subjected to a manufacturing process. The method includes generating a plurality of polygons that approximate geometries of the contours, respectively. The method includes associating each of the polygons with a respective one of a plurality of pattern elements in a pattern library, wherein the pattern elements each include a shape that resembles the associated polygon and electrical parameters extracted from the shape. The method includes calculating electrical performance of the circuit based on the pattern elements associated with the polygons.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuen-Yu Tsai, Wei-Jhih Hsieh, Bo-Sen Chang