Abstract: A process for completely removing TiN residue existing outside contact windows is described: electrical elements are formed on a silicon substrate, an insulating layer is then formed over the entire silicon substrate, next, the insulating layer is partially etched to form metal contact windows, a TiN barrier layer and a tungsten metal layer are then sequentially deposited overlaying the insulating layer and filling into the metal contact windows, two stage CMP process is performed to remove the metal and TiN barrier layers exposed outside the contact windows respectively, finally, an dry etching step employing HCl/Cl.sub.2 plasmas is performed to make sure there is not any TiN residues left outside contact windows.

Abstract: A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved.