Abstract: A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.

Abstract: A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.

Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

Abstract: A semiconductor device includes: a substrate; a first insulating film disposed on the substrate and having at least one via; and a second insulating film disposed on the first insulating film. The semiconductor device further includes: a first adhesion layer disposed on the first insulating film; a first conductive structure disposed in the at least one via and having an extended portion extending to a top surface of the first insulating film; and a second adhesion layer disposed on the first conductive structure. The first adhesion layer covers at least a part of a bottom surface of the extended portion, and the second adhesion layer covers at least a part of a top surface of the first conductive structure.

Abstract: An electronic device is provided. The electronic device includes an optical sensing module that includes an optical sensor array. The optical sensor array includes at least one optical sensor, at least one transparent layer disposed on the optical sensor array, and a microlens array. The microlens array includes at least one microlens and is disposed on the transparent layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.

Abstract: The present disclosure relates to the technical field of breeding, in particular to an environmental-friendly and efficient breeding method of high-yield and high-quality wheat cultivars. In the present disclosure, the breeding method can improve a breeding efficiency of excellent new cultivars, further realize large-scale production, and further increase a planting area of the excellent cultivars. In addition, the breeding method can increase the number of products for the new cultivars, further increase a diversity of early-generation materials, and further increase a diversity of hybrid samples through the innovation of hybridization and breeding methods. The environmental-friendly and efficient breeding method of high-yield and high-quality wheat cultivars can increase a richness of excellent characteristics of the new cultivars through high-generation materials, hybridization, and off-site identification, thereby further improving an effect of breeding.

Abstract: A cooling apparatus includes a casing, pumping unit, and heat exchange unit. The pumping unit includes a body and housing. The body includes a wishbone-shaped indentation and lollipop shaped indentation separate from the wishbone-shaped indentation. The housing includes a wishbone-shaped flow path and lollipop-shaped flow path separate from the wishbone-shaped flow path. The body is coupled to the housing such that the wishbone-shaped indentation and the wishbone-shaped flow path define a first flow path and the lollipop-shaped indentation and the lollipop-shaped flow path define a second flow path. The pumping unit is coupled to the heat exchange chamber such that the first flow path and the second flow path is in fluid communication with the heat exchange chamber via a first end opening and second end opening, and third opening, respectively.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.

Abstract: Disclosed are a compound serving as a PARP7 inhibitor, and a use thereof in preparing a drug for treating relevant diseases. Specifically disclosed are a compound represented by formula (I) and a pharmaceutically acceptable salt thereof. The compound can be used for treating cancer.

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

Abstract: A clinical therapeutic drug prediction and recommendation system (1) for evaluating the efficacy of a second-generation hormone drug in treatment of prostate cancer, comprising: an input device (10) used for receiving an ex vivo biological sample (40) and generating a physiological signal; a computer device (20) connected to the input device (10) and comprising a processor (201) used for receiving the physiological signal, said processor comprising an analysis module (2011) which compares at least the physiological signal with patient gene sets to which treatment by a first drug and a second drug are respectively applied, and then respectively obtains a first score and a second score corresponding to the first drug and the second drug by a computation method, the scores being further compared by a comparison module (2012), when the comparison result (20121) shows that the first score is greater than the second score, an indication (20131) of recommending the first drug to the individual being given, otherwise

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.

Abstract: An electronic device is provided. The electronic device includes a substrate, a first light-shielding layer, a second light-shielding layer, a third light-shielding layer and an optical sensing element. The first light-shielding layer is disposed on the substrate and has a first opening. The second light-shielding layer is disposed on the first light-shielding layer and has a second opening. The third light-shielding layer is disposed on the second light-shielding layer and has a third opening. The optical sensing element is disposed on the substrate, and overlapped with the first opening. In addition, in a top-view diagram, centers of the first opening, the second opening and the third opening are separated from each other along a first direction, and the first direction is a line connecting a center of the first opening and a center of the third opening.

Abstract: An electronic device are provided. The electronic device includes a display panel and an optical sensing module. The optical sensing module is disposed on a side of the display panel and includes an optical sensing layer, an optical assembly, and a light-blocking element. The optical assembly is disposed between the optical sensing layer and the display panel. The light-blocking element overlaps a portion of the optical sensing layer in a normal direction of the optical sensing layer. The optical assembly includes a plurality of light-blocking layers, and at least a portion of the plurality of light-blocking layers have different-sized openings.

Abstract: A method for analyzing an electrocardiography (ECG) signal is provided. The ECG signal is measured through a sensor. One or more specified waveforms in the ECG signal are detected. Multiple ECG features from each specified waveform are captured. The ECG features are input into multiple candidate models to obtain multiple candidate scores. Each candidate score is compared with a standard value to obtain an ideal score among the candidate scores. One of the candidate models corresponding to the ideal score is selected as a risk prediction model to predict disease risk through the risk prediction model.