Patents by Inventor Wei Ju
Wei Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141123Abstract: A manufacturing method of a modified polymer layer modified by hydroxyapatite is provided in the present disclosure, including following steps: (a) providing a polymer layer; (b) plasma-activating acrylic acid using an atmospheric cold plasma device to modify a surface of the polymer layer to obtain an acrylic-modified polymer layer; (c) immersing the acrylic-modified polymer layer in a first solution containing a calcium ion to obtain a calcium-containing modified layer; and (d) immersing the calcium-containing modified layer in a second solution containing phosphate salt to obtain a modified polymer layer modified by hydroxyapatite.Type: ApplicationFiled: June 9, 2023Publication date: May 2, 2024Inventors: Wei-Yu CHEN, Jui-Sheng LEE, Hui-Ju HSU
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Publication number: 20240139301Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.Type: ApplicationFiled: November 19, 2021Publication date: May 2, 2024Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
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Patent number: 11973425Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.Type: GrantFiled: December 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Chieh-Ju Tsai, Ching-Jan Chen, Zhen-Guo Ding, Zhe-Hui Lin, Wei-Ling Chen
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Patent number: 11973260Abstract: A light-transmitting antenna includes a substrate, a first and a second conductive pattern. The first and the second conductive pattern is disposed on a first and a second surface of the substrate respectively. The first conductive pattern includes a first feeder unit, a first and a second radiation unit, a first and a second coupling unit and a first parasitic unit. The first feeder unit is connected to the second radiation unit. The first and the second radiation unit are located between the first and the second coupling unit. One side and the other side of the first parasitic unit is connected to the second coupling unit and adjacent to the first coupling unit respectively. The second conductive pattern includes a second feeder unit, a third coupling unit, a second parasitic unit, and a fourth coupling unit.Type: GrantFiled: November 9, 2022Date of Patent: April 30, 2024Assignee: Industrial Technology Research InstituteInventors: Ruo-Lan Chang, Mei-Ju Lee, Cheng-Hua Tsai, Meng-Hsuan Chen, Wei-Chung Chen
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Patent number: 11972975Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.Type: GrantFiled: June 24, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
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Patent number: 11961913Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.Type: GrantFiled: April 21, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240120200Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
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Publication number: 20240120656Abstract: A light-transmitting antenna includes a substrate, a first conductive pattern, and a second conductive pattern. The first conductive pattern has a first feeder unit, a first radiation unit, a second radiation unit, and a first connection unit. The first feeder unit and the first connection unit are connected to two sides of the first radiation unit. The first connection unit connects the first radiation unit and the second radiation unit. The second conductive pattern has a second feeder unit, a third radiation unit, a fourth radiation unit, and a second connection unit. The second feeder unit and the second connection unit are connected to two sides of the third radiation unit. The second connection unit connects the third radiation unit and the fourth radiation unit. An orthogonal projection of the second feeder unit on a first surface of the substrate at least partially overlaps the first feeder unit.Type: ApplicationFiled: December 22, 2022Publication date: April 11, 2024Applicant: Industrial Technology Research InstituteInventors: Meng-Hsuan Chen, Cheng-Hua Tsai, Mei-Ju Lee, Ruo-Lan Chang, Wei-Chung Chen
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Patent number: 11953372Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.Type: GrantFiled: January 18, 2022Date of Patent: April 9, 2024Assignee: InnoLux CorporationInventors: Yu-Tsung Liu, Wei-Ju Liao, Wei-Lin Wan, Cheng-Hsueh Hsieh, Po-Hsin Lin, Te-Yu Lee
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Publication number: 20240114454Abstract: Various solutions for low-power wake-up signal (LP-WUS) design with respect to user equipment and network node in mobile communications are described. An apparatus may receive a LP-WUS configuration from a network node. The apparatus may receive a LP-WUS based on the LP-WUS configuration from the network node. The apparatus may determine whether to wake up according to the LP-WUS. The LP-WUS with N subcarriers (SCs) is generated through a transformation of M-bit on-off keying (OOK) in a time domain. The transformation is a discrete Fourier transform (DFT) or least square operation. K samples are generated from the M bits with a signal modification or a signal truncation. The LP-WUS is generated through an inverse fast Fourier transform (IFFT) operation. The K is a size of the IFFT operation of cyclic-prefix orthogonal frequency-division multiple access (CP-OFDMA). The N is less than or equal to the K.Type: ApplicationFiled: August 22, 2023Publication date: April 4, 2024Inventors: Chien-Chun Cheng, Wei-De Wu, Yi-Ju Liao
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Publication number: 20240113173Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.Type: ApplicationFiled: November 27, 2023Publication date: April 4, 2024Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20240095141Abstract: A method and an apparatus for displaying an information flow on a terminal device, an electronic device, a computer-readable storage medium, and a computer program product are provided. An implementation is: in response to detecting an activation operation on an application for displaying the information flow, reproducing, on the terminal device, a first page displayed on the terminal device when the application is last switched to running in the background or closed; and in response to determining that a time interval between the activation operation and the application being last switched to running in the background or closed does not exceed a first threshold, displaying a second page as a continuation of a content entry displayed in the first page, where the second page includes at least one first content entry cached in the terminal device before the activation operation but not displayed in the first page.Type: ApplicationFiled: March 21, 2022Publication date: March 21, 2024Inventors: Yifan ZHANG, Yuqi WANG, Linfei CHU, Jing NING, Kunjie SUN, Yuhang ZHENG, Naifei SONG, Shujuan ZHANG, Lin LIU, Xunzhuo JU, Zhengwei CHEN, Wei ZHANG, Hua ZHANG, Congjun ZHOU, Tingkang WU, Tengfei LV, Hanmeng LIU, Lei WANG
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Patent number: 11931363Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.Type: GrantFiled: October 19, 2021Date of Patent: March 19, 2024Assignee: NOVARTIS AGInventors: Ho Man Chan, Xiang-Ju Justin Gu, Ying Huang, Ling Li, Yuan Mi, Wei Qi, Martin Sendzik, Yongfeng Sun, Long Wang, Zhengtian Yu, Hailong Zhang, Ji Yue (Jeff) Zhang, Man Zhang, Qiong Zhang, Kehao Zhao
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Publication number: 20240088969Abstract: This disclosure relates to techniques for a wireless device to perform channel state information reporting. The wireless device may receive channel state information reporting configuration information. The channel state information reporting configuration information may include an indication to use a wideband precoding matrix indicator format for 3GPP release 16 type II channel state information reporting. The wireless device may perform channel state information reporting using a different reporting configuration than 3GPP release 16 type II channel state information reporting using a wideband precoding matrix indicator format based at least in part on the channel state information reporting configuration information. The wireless device may also or alternatively perform 3GPP type I channel state information reporting using a unified spatial basis selection framework for rank indicators of 3 and 4 for any number of channel state information reference signal ports.Type: ApplicationFiled: November 6, 2023Publication date: March 14, 2024Inventors: Haitong Sun, Yushu Zhang, Wei Zeng, Dawei Zhang, Ghaith N. Hattab, Ismael Gutierrez Gonzalez, Anchit Malhotra, Louay Jalloul, David Neumann, Ziyang Ju
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Publication number: 20240081352Abstract: The present disclosure provides a blending method of high-quality and dual-purpose flour for bread and noodles, belonging to the technical field of flour processing. The method includes: selecting flour of a high-quality and dual-purpose wheat variety for bread and noodles as a high-quality basic flour for blending; according to a large gradient experimental design, selecting a gradient range ratio with a sedimentation value ?46.0 mL and a dough development time ?9.6 min, followed by subdividing for small gradient experiments; selecting a ratio with flour sedimentation value and dough development time that reach an ideal value to blend a large amount of flour; and making bread and noodles for scoring, followed by determining a blending ratio if a scoring result reaches an ideal value.Type: ApplicationFiled: September 11, 2022Publication date: March 14, 2024Inventors: Yan Zi, Jianmin Song, Xiao Ma, Aifeng Liu, Wei Ju, Haosheng Li, Dungong Cheng, Canguo Wang, Jun Guo, Jianjun Liu, Xinyou Cao, Cheng Liu, Shengnan Zhai, Faji Li, Ran Han, Zhendong Zhao
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Patent number: 11929409Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; aType: GrantFiled: October 14, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Publication number: 20240071988Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.Type: ApplicationFiled: October 11, 2022Publication date: February 29, 2024Inventors: Kun-Ju LI, Hsin-Jung LIU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU
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Publication number: 20240065489Abstract: In various embodiments, a washable mat system comprises a top cover removably attached to a bottom pad. The top cover comprises layers of material, including a top layer with a tufted loop pile, a water-resistant internal layer, and a bottom knit surface. The top cover is sufficiently malleable to be folded, rolled, compressed, and withstand multiple wash and dry cycles while maintaining material stability. The bottom pad also comprises layers of material, including a top layer to removably attach to the bottom knit surface of the top cover, an internal cushioning layer, and a non-slip bottom surface.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: Ruggable LLCInventors: Lydia Wei-Ju Chen, Leonard John Duran, William Stanhope St. Amant, Robert Westphal Vera, Therese Mona-Lisa Germain, Max Flanders Sieck
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Patent number: 11915943Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.Type: GrantFiled: October 25, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee