Abstract: A display memory architecture which efficiently stores and processes true color and index mode pixels is disclosed. The R, G and B components of true color mode pixels occupy different groups of bit planes in different banks of a frame memory. In addition, consecutive index mode pixels are located in not necessarily consecutive different groups of bit planes in consecutive banks so that a plurality of index mode pixels can be accessed simultaneously in reading and writing operations. Pixel swap circuits are used to swap the order of the R, G and B components of true color pixels and the order of simultaneously accessed index mode pixels, when the order of the accessed locations is different from the order in which R, G and B components of true color pixels or a plurality of index mode pixels are processed by a graphics processor.

Abstract: A computer graphics system comprises a main CPU, a main system memory and a graphics subsystem for displaying graphical images on a display terminal. A system bus enables the main CPU, main system memory and graphics subsystem to transmit data among one another. The graphics subsystem comprises a graphics controller in communication with the system bus, a frame buffer for storing pixels displayed on the display terminal, and a separate off-screen memory unit located within the graphics subsystem for storing off-screen pixels in a linear format. A local bus is included in the graphics subsystem for transmitting data within the graphics subsystem among the frame buffer, the off-screen memory and the graphics controller. The graphics controller includes an address processing unit for converting between two-dimensional addresses and linear format addresses utilized by the off-screen memory unit.

Abstract: A controller and method for refreshing a display device with data linearly stored in a video memory having a row addressable memory array and serial access memory are disclosed. The circuit for controlling the video memory includes a row address generator for addressing a row of data in the memory array. A circuit is provided for initiating a split row transfer of a half addressed row of the memory array to the corresponding half of the serial access memory while data are shifted out of the other half of the serial access memory. A tap pointer generator is also provided to alternatively point to the different halves of the memory array rows.

Abstract: An address processing unit for use in a graphics controller is disclosed. The address processing means performs a variety of address processing functions including conversion between two-dimensional and linear addresses.