Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point.

Abstract: Semiconductor device and method of forming the same are disclosed. One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern has at least one turning point.

Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: A system and method for performing circuit design analysis obtains a circuit design comprising cells. The cells are associated with cell types. Aging parameters of a core analytical model are determined for each of the cell types in the circuit design to generate a calibrated analytical model. Aging effects for the cells are determined based on the calibrated analytical model and target stress conditions. An aged timing model is determined for the cell types based on the aging effects, an unaged timing model, and the target stress conditions.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: Semiconductor device and method of forming the same are disclosed. One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern has at least one turning point.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

Abstract: An MOS varactor may be formed without tip implants or HALO implants. As a result, parasitic resistance may be reduced, jitter may be improved, and the quality factor may be increased, as well as the tunable range of the varactor.

Abstract: A metal oxide semiconductor varactor may be formed with HALO implants regions having an opposite polarity from the polarity of the well of the varactor. The HALO implant regions can be angled away from the source and drain. The HALO implant regions can stop the depletion from continuing as the bias voltage applied to the gate continues to increase. Stopping that depletion can create a constant capacitance when the varactor is in a depletion bias.

Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.