Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: A management method for a data storage device is provided and includes the following steps: obtaining a plurality of association rules according to a plurality of previous access commands; building a plurality of look-up tables according to the association rules; receiving a current access command and determining whether the current access command corresponds to at least one of the look-up tables to obtain physical addresses of the current access command from the corresponding look-up table; predicting a look-up table corresponding to a subsequent access command based on these association rules; and pre-establishing the predicted look-up tables. The invention also provides a data storage system and a data storage device, which can implement the management method described above.

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: A disk managing method includes: receiving a host Frame Information Structure (FIS) including multiple host logical Block Address Range Entries (LBA Range Entries) from a host; determining whether the LBA Range Entries satisfy a speed up processing condition; generating a first and a second addresses corresponding to a first and a second hard disks according to the host LBA Range Entries; and outputting a first and a second hard disk FIS to the first and the second hard disk for management. The number of first and second hard disk LBA Range Entries in the first and the second hard disk FIS are respectively half of the number of the host LBA Range Entries.

Abstract: A disk managing method includes: receiving a host Frame Information Structure (FIS) including multiple host logical Block Address Range Entries (LBA Range Entries) from a host; determining whether the LBA Range Entries satisfy a speed up processing condition; generating a first and a second addresses corresponding to a first and a second hard disks according to the host LBA Range Entries; and outputting a first and a second hard disk FIS to the first and the second hard disk for management. The number of first and second hard disk LBA Range Entries in the first and the second hard disk FIS are respectively half of the number of the host LBA Range Entries.

Abstract: A port multiplier system is provided. The port multiplier system comprises a first port multiplier and a second port multiplier. The first port multiplier is configured to receive a plurality of first frame information structures from a host. Each of the first frame information structure corresponds to a first port multiplier port number. The first port multiplier sends the first frame information structures that correspond to the first port multiplier port numbers, respectively, to a first downstream port of the first port multiplier according to first port multiplier port number. The second port multiplier is configured to send the first frame information structures that are sent to the first downstream port to a plurality of second downstream ports of the second port multiplier, respectively. An operation method is also provided.

Abstract: A port multiplier system is provided. The port multiplier system comprises a first port multiplier and a second port multiplier. The first port multiplier is configured to receive a plurality of first frame information structures from a host. Each of the first frame information structure corresponds to a first port multiplier port number. The first port multiplier sends the first frame information structures that correspond to the first port multiplier port numbers, respectively, to a first downstream port of the first port multiplier according to first port multiplier port number. The second port multiplier is configured to send the first frame information structures that are sent to the first downstream port to a plurality of second downstream ports of the second port multiplier, respectively. An operation method is also provided.

Abstract: A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.

Abstract: A flash memory control apparatus having a sequential writing procedure and method thereof are described. The flash memory control apparatus includes primary controller, a command module, an address module, a data buffer, a status unit, a counting device and a secondary controller. The primary controller generates a predetermined value which represents the amount of a plurality of pages in the flash memory. The command module stores a writing command during the writing procedure. The address module stores a current address for addressing a current page of the pages based on the current address and the writing command via a control bus. The data buffer stores the data for allowing the command module to write the data to the current page based on the current address via the control bus while the writing command is executed on the flash memory. The status unit determines that the flash memory is either ready or busy in writing the data to the current page of the flash memory.