Abstract: Within a method for forming a spin-on-glass (SOG) layer there is first provided a substrate. There is then formed over the substrate a spin-oil-glass (SOG) planarizing layer while employing a silsesquioxane spin-on-glass (SOG) planarizing material. There is then annealed thermally the spin-on-glass (SOG) planarizing layer while employing a first thermal annealing method employing a first gaseous atmosphere comprising a non-oxidizing gas to form a cured spin-on-glass (SOG) planarizing layer. Finally, there is then annealed thermally the cured spin-on-glass (SOG) planarizing layer while employing a second thermal annealing method employing a second gaseous atmosphere comprising an oxidizing gas to form firm the cured spin-on-glass (SOG) planarizing layer an oxidized cured spin-on-glass (SOG) planarizing layer.

Abstract: A process for reducing the dark current generation of an image sensor cell, fabricated on a semiconductor substrate, has been developed. The process features the use of polysilicon pad structure, formed simultaneously with a polysilicon gate structure of a reset transistor, with the polysilicon pad structure located overlying, and contacting, a portion of the top surface of the photodiode element, of the image sensor cell. A small diameter opening, in a composite polysilicon-silicon oxide layer, exposes the portion of photodiode element to be contacted by the polysilicon pad structure. The small diameter opening is created using a procedure which allows the surface of the photodiode element, exposed in the small diameter opening to experience only a minimum of RIE processing at end point, thus minimizing damage to the surface of the photodiode element, and thus reducing dark current generation.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures, with an extended region for source drains bordering photodiode regions. Ions are implanted to form photodiodes, overlapping the extended bordering source drain regions. A blanket transparent insulating layer is deposited.

Abstract: A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

Abstract: A method and means for testing binary code devices, such as ROMs, for correct coding during processing with the Process Control Machine (PCM) for the fabrication process by applying it on the scribe-line built-in binary code devices, and using the testing program to measure the threshold voltage VTN of the code devices and convert the binary signal sensed to a decimal number to identify the ROM code id. After finishing wafer processing and PCM testing, the real ROM code id that has been fabricated can be read from the PCM testing report.

Abstract: A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.

Abstract: A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer.

Abstract: A new method of forming a high quality silicon oxide under a gate electrode for an integrated circuit is described. A gate silicon oxide layer is formed for the gate electrode. A blockout mask is provided for all areas of the integrated circuit not requiring an ion implant. The ion implant is implanted through the gate silicon oxide layer into those areas not covered by the blockout mask. The blockout mask is removed. The gate silicon oxide layer is cleaned to improve the electrical breakdown and charge breakdown characteristics to the state they were before the mask and ion implanting steps by a) treating the gate silicon oxide layer with ammonia and peroxide fluid in the concentration NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=(0.4-1):1:5.5 for between about 3 to 7 minutes at a temperature of between about 60.degree. to 80.degree. C. and b) subjecting the gate silicon oxide layer to an atmosphere of C.sub.2 H.sub.2 Cl.sub.2 and excess oxygen at a temperature of between about 775.degree. to 875.degree. C.