Patents by Inventor Wei-Kung Tsai
Wei-Kung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9343352Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.Type: GrantFiled: January 23, 2015Date of Patent: May 17, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
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Publication number: 20160099169Abstract: The methods for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.Type: ApplicationFiled: December 16, 2015Publication date: April 7, 2016Inventors: Kuo-Yu CHENG, Keng-Yu CHEN, Wei-Kung TSAI, Kuan-Chi TSAI, Tsung-Yu YANG, Chung-Long CHANG, Chun-Hung CHEN, Chih-Ping CHAO
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Patent number: 9230988Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.Type: GrantFiled: October 31, 2013Date of Patent: January 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yu Cheng, Keng-Yu Chen, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao
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Publication number: 20150206902Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHENG, Keng-Yu CHEN, Wei-Kung TSAI, Kuan-Chi TSAI, Tsung-Yu YANG, Chung-LONG CHANG, Chun-Hung CHEN, Chih-Ping CHAO
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Publication number: 20150206964Abstract: In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHENG, Wei-Kung TSAI, Kuan-Chi TSAI
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Patent number: 9048287Abstract: Embodiments of mechanisms for forming a semiconductor device structure with floating spacers are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate and a gate stack formed on the SOI substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack. The gate spacers include a floating spacer. The semiconductor device structure further includes a contact etch stop layer formed on the gate stack and the gate spacers. The contact etch stop layer is formed between the floating spacer and the SOI substrate.Type: GrantFiled: November 15, 2013Date of Patent: June 2, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai
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Publication number: 20150137234Abstract: Embodiments of mechanisms for forming a semiconductor device structure with floating spacers are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate and a gate stack formed on the SOI substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack. The gate spacers include a floating spacer. The semiconductor device structure further includes a contact etch stop layer formed on the gate stack and the gate spacers. The contact etch stop layer is formed between the floating spacer and the SOI substrate.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHENG, Wei-Kung TSAI, Kuan-Chi TSAI
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Publication number: 20150132918Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
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Publication number: 20150115381Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHENG, Keng-Yu CHEN, Wei-Kung TSAI, Kuan-Chi TSAI, Tsung-Yu YANG, Chung-LONG CHANG, Chun-Hung CHEN, Chih-Ping CHAO
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Publication number: 20150108607Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yu CHEN, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Patent number: 8941211Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.Type: GrantFiled: March 1, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
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Patent number: 6946391Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.Type: GrantFiled: September 8, 2003Date of Patent: September 20, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Wei-Kung Tsai, Po-Yueh Tsai
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Publication number: 20050092255Abstract: An edge-contact wafer holder which is suitable for holding wafers as the wafers are loaded onto and unloaded from a processing tool such as a CMP (chemical mechanical planarization) apparatus, for example. The edge-contact wafer holder includes a typically ring-shaped holder body which is mounted typically on a load cup on a HCLU (Head Clean Load/Unload) station of a CMP apparatus and supports each individual wafer at or near the wafer edge. Multiple guide pins may extend upwardly from the holder body to guide each wafer onto the holder body as the wafer is lowered in place onto the holder body.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Inventors: Feng-Jung Chang, Poyueh Tsai, Feng-Yu Kuo, Wei-Kung Tsai
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Publication number: 20050054194Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.Type: ApplicationFiled: September 8, 2003Publication date: March 10, 2005Inventors: Wei-Kung Tsai, Po-Yueh Tsai