Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.

Abstract: A vertically alternating sequence of insulating layers and sacrificial material layers is formed over a substrate. Line trenches extending along a first horizontal direction are formed through the vertically alternating sequence. The vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips. Laterally alternating sequences of memory opening fill structures and dielectric pillar structures are formed within the line trenches. Each of the memory opening fill structures includes a respective vertical bit line and memory material portion located between each laterally neighboring pair of the sacrificial material strip and the vertical bit line.

Abstract: An image processing method for processing a first image captured by a camera is provided, in which the first image is retrieved; and an output image is output to an image output circuit after the first image is modified to the output image, wherein a result value of each pixel of the output image is zero or a value generated by subtracting the threshold value from the brightness value of each pixel of the first image.

Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Protruding tip portions are formed on each of the sacrificial material layers around the memory openings. A plurality of insulating spacers is formed within each memory opening between each vertically neighboring pair of tip portions of the sacrificial material layers. A phase change memory material and a vertical bit line are formed within each of the memory openings. The phase change memory material can be formed as a vertical stack of discrete annular phase change memory material portions, or can be formed as a continuous phase change memory material layer. Each of the sacrificial material layer can be replaced by an electrically conductive layer.

Abstract: A vertically alternating sequence of insulating layers and sacrificial material layers is formed over a substrate. Line trenches extending along a first horizontal direction are formed through the vertically alternating sequence. The vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips. Laterally alternating sequences of memory opening fill structures and dielectric pillar structures are formed within the line trenches. Each of the memory opening fill structures includes a respective vertical bit line and memory material portion located between each laterally neighboring pair of the sacrificial material strip and the vertical bit line.

Abstract: First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.

Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.

Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.

Abstract: A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

Abstract: The disclosure provides an augmented reality (AR) device, a notebook, and smart glasses. The AR device includes a laser source, a spatial light modulator (SLM), and a hologram optical element (HOE). The laser source provides a coherent laser ray. The SLM provides a diffraction pattern solely corresponding to the coherent laser ray. When the SLM receives the coherent laser ray, the diffraction pattern diffracts the coherent laser ray as a hologram in response to the coherent laser ray. The HOE provides a concave mirror effect merely in response to a wavelength of the coherent laser ray, wherein the HOE receives the hologram and magnifies the hologram as a stereoscopic virtual image.

Abstract: An eye tracker includes a lens, a beam splitter, a structured light source and an image capturing element. The beam splitter is disposed at one side of the lens. The structured light source and the image capturing element are disposed between the lens and the beam splitter. The structured light source is configured to emit a first light and project to the beam splitter. The first light is reflected to the lens from the beam splitter and passes through the lens to project to an eye. The first light is reflected from the eye to form a second light. The second light passes through the lens and projects to the beam splitter, and is reflected to the image capturing element from the beam splitter. A display is also provided.

Abstract: A head mounted display includes a body portion, a display panel, a lens module, an infrared transmitter, and an infrared receiver. The display panel is provided in the body portion. The lens module is disposed in front of the display panel, and includes an outer frame, a lens and a mounting portion. The lens is provided in the outer frame. The mounting portion is disposed at the periphery of the outer frame. A reference line is connected between the viewing point and the mounting portion. The infrared transmitter is disposed on the mounting portion. The outer frame is provided with a light exit surface between the viewing point and the mounting portion. The infrared transmitter projects a light along the reference line via the light exit surface which limits the exit angle of the light. The infrared receiver is disposed on the body portion for receiving the light.

Abstract: A computer system, a game loading method thereof and a computer readable storage medium are provided. The computer system includes a first storage, a second storage and a processor. The first storage stores multiple game files of a game. The access rate of the second storage is faster than the first storage. The processor is coupled to the first and second storages. The processor performs the game, stores corresponding game files in the first storage into the second storage according to process of the game, and access the game files stored in the second storage to continue progress of the game. Accordingly, loading time of game scene can be reduced, so as to improve gaming experience.

Abstract: An image processing method for processing a first image captured by a camera is provided, in which the first image is retrieved; and an output image is output to an image output circuit after the first image is modified to the output image, wherein a result value of each pixel of the output image is zero or a value generated by subtracting the threshold value from the brightness value of each pixel of the first image.

Abstract: An image processing method for processing a first image captured by a camera is provided, in which the first image is retrieved; and an output image is output to an image output circuit after the first image is modified to the output image, wherein a result value of each pixel of the output image is zero or a value generated by subtracting the threshold value from the brightness value of each pixel of the first image.

Abstract: A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

Abstract: A virtual reality display apparatus includes at least one display and at least one optical assembly. The display provides an image beam to a left eye or a right eye of a user. The optical assembly is disposed on a transmission path of the image beam and located between the left eye or the right eye of the user and the display. The optical assembly includes at least one Fresnel lens including ring structures surrounding an optical axis thereof. Each of the ring structures includes an effective refraction surface and an optically non-effective surface connected to each other and arranged along a radial direction. A junction of the effective refraction surface and the optically non-effective surface has a round angle. The radius of curvature of the round angles of at least some of the ring structures of the Fresnel lens is smaller than 10 ?m and larger than 0 ?m.

Abstract: A chroma aberration compensation method using sub-pixel shifting for use in a head-mounted display is provided. The method includes the steps of: obtaining image data from a host, wherein the image data includes a left-eye image and a right-eye image; obtaining a refraction characteristics curve corresponding to a left-eye lens and a right-eye lens and calculating a resolution of the image data; calculating a distance and a relative direction between each sub-pixel in each color channel of the image data and a center of the image data; adjusting an offset value of each sub-pixel in each color channel of the image data according to the calculated distance and relative direction; performing a sub-pixel shifting compensation process to adjust a sub-image corresponding to each color channel to generate an output image according to the offset value of each sub-pixel in each color channel of the image data.

Abstract: An image capturing device is provided. The image capturing device includes an image sensing circuit, a determination circuit and an output circuit. The image sensing circuit is utilized for capturing a first test image at a first time point and capturing a second test image at a second time point. The determination circuit is utilized for calculating a first image feature value associated with a color value of the first test image and a second image feature value associated with a color value of the second test image, calculating a difference value between the first image feature value and the second image feature value and comparing the difference value with a threshold value to generate a determination result. The output circuit is utilized for outputting the images generated by the image capturing device according to the determination result.