Patents by Inventor Wei Leong TAN

Wei Leong TAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411175
    Abstract: A method for manufacturing a semiconductor package assembly is provided. The assembly includes a semiconductor package and a molding resin case encapsulating the semiconductor package. The complete semiconductor package undergoes a surface roughening treatment, thus improving the overall adhesion with the molding resin (EMC) and reducing the risks of delamination.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 21, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Wai Wai Lee, Ting Wei Chang, Jia Yunn Ting, Wei Leong Tan
  • Publication number: 20230402355
    Abstract: An electronic package and a method for manufacturing the same is provided. The electronic package includes a first substrate, an electronic component arranged on and/or formed in the first substrate, a thermally conductive second substrate including a first portion and a second portion integrally connected to the first portion, and at least the first portion among the first and second portion is fixedly attached to the electronic component, and a package material arranged to encapsulate the electronic component and to at least partially encapsulate the first and second substrate, and the package material includes a recess formed therein that extends up to a surface of the first portion.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Wei Leong Tan, Wai Wai Lee, Hing Suan Cheam
  • Publication number: 20230326835
    Abstract: Aspects of the present disclosure relate to a molded electronic package and a method for manufacturing the same. The molded electronic package includes a first substrate, a second substrate, an electronic component arranged on the first substrate, a spring member arranged between the second substrate and the electronic component, the spring member including a first contact portion being fixated relative to the second substrate, and a second contact portion physically contacting the electronic component, and a body of solidified molding compound configured to encapsulate the electronic component and the spring member and to mutually fixate the first substrate, the second substrate, the electronic component and the spring member. The second substrate and the spring member are electrically and/or thermally conductive.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Hing Suan Cheam, Wei Leong Tan, Ting Wei Chang
  • Patent number: 11728179
    Abstract: A surface mount semiconductor device and method of manufacture. A semiconductor die is mounted on a first support surface; a leadframe is attached to the semiconductor die, the leadframe comprising: an electrical lead having a first lead region connected to the semiconductor die; and a second lead region distal the first lead region, wherein the second lead region is connected to a second support surface; encapsulating the semiconductor die, first support surface and the first lead region; the second lead region is severed from the second support surface to expose a lead end; and the second lead region is electro-plated with a metallic material, such that the lead end is coated with said metallic material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 15, 2023
    Assignee: Nexperia B.V.
    Inventors: Ricardo Yandoc, Adam Richard Brown, Haibo Fan, Kow Siew Ting, Nam Khong Then, Wei Leong Tan
  • Publication number: 20190067033
    Abstract: A surface mount semiconductor device and method of manufacture. A semiconductor die is mounted on a first support surface; a leadframe is attached to the semiconductor die, the leadframe comprising: an electrical lead having a first lead region connected to the semiconductor die; and a second lead region distal the first lead region, wherein the second lead region is connected to a second support surface; encapsulating the semiconductor die, first support surface and the first lead region; the second lead region is severed from the second support surface to expose a lead end; and the second lead region is electro-plated with a metallic material, such that the lead end is coated with said metallic material.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Inventors: Ricardo YANDOC, Adam Richard BROWN, Haibo FAN, Kow Siew TING, Nam Khong THEN, Wei Leong TAN