Patents by Inventor Wei-Li Chen
Wei-Li Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962441Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: GrantFiled: July 25, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 11953955Abstract: A fixing mechanism is applied to an interface card assembly and an electronic apparatus. The fixing mechanism includes a movable window and an operation component. The movable window is slidably disposed on a casing of the interface card assembly. The operation component has a fixed end and a free end opposite to each other. The fixed end is disposed on the movable window. The free end is detachably engaged with the casing to position the movable window. The movable window is positioned on one of a first region and a second region of the casing for respectively fixing interface cards with different sizes to the casing.Type: GrantFiled: November 9, 2021Date of Patent: April 9, 2024Assignee: Wiwynn CorporationInventors: Wei-Li Huang, Wei-Hao Chen
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Publication number: 20240087057Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.Type: ApplicationFiled: December 20, 2022Publication date: March 14, 2024Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Ke-Li WU, Hua-Hsiu CHIANG, Yu-Lun CHANG
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Patent number: 11883932Abstract: A claw assembly includes a collar, claws and a synchronizer. The collar includes slots. The claws are pivotally connected to the collar. Each of the claws includes a protuberance extending into the collar via one of the slots. The protuberances are movable along the slots. The synchronizer includes a receiving portion for receiving the protuberances. The receiving portion of the synchronizer is movable in the collar between an opening position and a closing position. The synchronizer opens the claws by the protuberances in the opening position. The synchronizer closes the claws by the protuberances in the closing position.Type: GrantFiled: August 27, 2021Date of Patent: January 30, 2024Inventors: Yi-Fang Chen, Wei-Li Chen
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Patent number: 11679476Abstract: A puller includes a collar, claws, a synchronizer and an abutting element. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The abutting element is extensible from the collar.Type: GrantFiled: March 26, 2021Date of Patent: June 20, 2023Inventors: Yi-Fang Chen, Wei-Li Chen
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Publication number: 20220360476Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 11398933Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: GrantFiled: February 1, 2021Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Publication number: 20220152800Abstract: A puller includes a collar, claws, a synchronizer and an abutting assembly. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The synchronizer is extensible from the collar.Type: ApplicationFiled: March 26, 2021Publication date: May 19, 2022Inventors: Yi-Fang Chen, Wei-Li Chen
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Publication number: 20220152799Abstract: A puller includes a collar, claws, a synchronizer and an abutting element. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The abutting element is extensible from the collar.Type: ApplicationFiled: March 26, 2021Publication date: May 19, 2022Inventors: Yi-Fang Chen, Wei-Li Chen
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Publication number: 20220152798Abstract: A claw assembly includes a collar, claws and a synchronizer The collar includes slots. The claws are pivotally connected to the collar. Each of the claws includes a protuberance extending into the collar via one of the slots. The protuberances are movable along the slots. The synchronizer includes a receiving portion for receiving the protuberances. The receiving portion of the synchronizer is movable in the collar between an opening position and a closing position. The synchronizer opens the claws by the protuberances in the opening position. The synchronizer closes the claws by the protuberances in the closing position.Type: ApplicationFiled: August 27, 2021Publication date: May 19, 2022Inventors: Yi-Fang Chen, Wei-Li Chen
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Publication number: 20220152797Abstract: A puller includes a collar, claws, a synchronizer and a threaded rod. The collar includes a space, a screw hole in communication with the space, slots in communication with the space, and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The threaded rod is inserted in the screw hole of the collar.Type: ApplicationFiled: March 26, 2021Publication date: May 19, 2022Inventors: Yi-Fang Chen, Wei-Li Chen
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Publication number: 20220158878Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11240075Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: GrantFiled: January 25, 2021Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11183262Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.Type: GrantFiled: April 17, 2020Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Ruei Li, Fan-Ming Kuo, Wei-Li Chen
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Publication number: 20210327528Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Ruei Li, Fan-Ming Kuo, Wei-Li Chen
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Publication number: 20210305131Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: Yu-Hung Cheng, Shih-Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen
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Publication number: 20210218605Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 25, 2021Publication date: July 15, 2021Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11049797Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.Type: GrantFiled: April 15, 2016Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hung Cheng, Shih-Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen
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Publication number: 20210160107Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 11017149Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.Type: GrantFiled: May 11, 2020Date of Patent: May 25, 2021Inventors: Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee