Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: In one embodiment of the present invention, a signal sampling method is provided. It comprises: (a) sampling an input signal with respect to a sampling clock signal; (b) calculating a maximum transition timing and a minimum transition timing of the input signal according to a relation between the sampling in step (a) and a reference timing clock; (c) defining a voltage level transition interval according to the maximum transition timing and the minimum transition timing; and (d) determining phase of the sampling clock signal or phase of the input signal according to the voltage level transition interval.

Abstract: In one embodiment of the present invention, a signal sampling method is provided. It comprises: (a) sampling an input signal with respect to a sampling clock signal; (b) calculating a maximum transition timing and a minimum transition timing of the input signal according to a relation between the sampling in step (a) and a reference timing clock; (c) defining a voltage level transition interval according to the maximum transition timing and the minimum transition timing; and (d) determining phase of the sampling clock signal or phase of the input signal according to the voltage level transition interval.