Patents by Inventor Wei Lian Goay

Wei Lian Goay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8863061
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: October 14, 2014
    Assignee: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Publication number: 20130314122
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 28, 2013
    Applicant: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Patent number: 8504963
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 6, 2013
    Assignee: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Publication number: 20130002295
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: ALTERA CORPORATION
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Patent number: 8291355
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 16, 2012
    Assignee: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Publication number: 20110084727
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 14, 2011
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
  • Patent number: 7870513
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 11, 2011
    Assignee: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay