Abstract: An adaptive integrated circuit (IC) testing method includes acquiring mass production data of a plurality of ICs, analyzing the mass production data by a training model for generating predicted data of the plurality of ICs, partitioning the plurality of ICs into at least two IC groups according to the predicted data, and adjusting at least two testing processes according to the at least two IC groups. The at least two IC groups are non-overlapped.

Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).

Abstract: A testing method for use in semiconductor device testing, includes: performing at least one test item from a set of test items on a semiconductor device under a first environmental condition; generating, via a machine learning model and based on a test result of the at least one test item, a qualification result predictive of at least one test result for one or more test items from the set of test items when performed on the semiconductor device under a second environmental condition; and determining, based on the qualification result, whether to perform the one or more test items from the set of test items on the semiconductor device under the second environmental condition.

Abstract: A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature based on the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature.

Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).