Patents by Inventor WEI-LIN HSU

WEI-LIN HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12197737
    Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 14, 2025
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Yu-Cheng Hsu, Wei Lin
  • Patent number: 12189251
    Abstract: A signal control method suitable for a touch screen is provided. The signal control method comprises: switching a plurality of scan lines to an enabling voltage level sequentially in a display stage; turning on a plurality of switches sequentially to transmit a plurality of display data to a plurality of data lines when a first scan line of the plurality of scan lines is in an enabled voltage level, wherein a first switch of the plurality of switches is coupled to a first data line of the plurality of data lines, and the first data line corresponds to one of a plurality of dummy lines in a vertical direction, when the first scan line is in the enabled voltage level, the first switch is turned on after other switches are turned on; and setting the plurality of dummy lines to a touch voltage in a touch stage.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: January 7, 2025
    Assignee: AUO CORPORATION
    Inventors: Shih-Hsi Chang, Yu-Hsin Ting, Chung-Lin Fu, I-Fang Chen, Wei-Chun Hsu, Nan-Ying Lin
  • Publication number: 20240365563
    Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 31, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Publication number: 20240355859
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first IC chip includes a plurality of photodetectors disposed in a first substrate and a first bond structure. The first bond structure includes a first plurality of bond contacts disposed on a first plurality of conductive bond pads. The second IC chip includes a second bond structure and a second substrate. A first bond interface is disposed between the first bond structure and the second bond structure. The second bond structure comprises a second plurality of bond contacts. The first bond structure further includes a first plurality of shield structures disposed between adjacent conductive bond pads in the first plurality of conductive bond pads.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240347576
    Abstract: Various embodiments of the present disclosure relate to an interstitial stacked-integrated-circuit interface shielding structure. A first integrated circuit (IC) chip includes a first dielectric layer. A second IC chip is bonded to the first IC chip at a bond interface and includes a second dielectric layer directly contacting the first dielectric layer at the bond interface. A first pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A second pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A pair of shield structures are respectively in the first and second dielectric layers and directly contact at the bond interface. Further, the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240339475
    Abstract: Some embodiments relate to an IC device, including a first chip; and a second chip bonded to the first chip at a bonding interface; where the first and second chips respectively comprise a first dielectric layer and a second dielectric layer directly contacting; the first chip further comprises a plurality of conductive pads recessed into the first dielectric layer and in a plurality of rows and columns; where the plurality of conductive pads are arranged with a zig-zag layout along the plurality of columns and along the plurality of rows and comprise a first conductive pad and a second conductive pad; the first chip further comprises a first shield line in the first dielectric layer and laterally between the first and second conductive pads, and the second chip further comprises a contact recessed into the second dielectric layer and directly contacting the first conductive pad at the bonding interface.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240339467
    Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Chia-Chi Hsiao, Kuan-Chieh Huang, Wei-Cheng Hsu, Hao-Lin Yang, Yi-Han Liao, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240332333
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first chip IC includes a first bond structure. The first bond structure includes a first plurality of conductive bond pads and a first plurality of shield structures disposed between adjacent conductive bond pads among the first plurality of conductive bond pads. The second IC chip includes a second bond structure. A bonding interface is disposed between the first bond structure and the second bond structure. The second bond structure includes a second plurality of conductive bond pads and a second plurality of shield structures. The first plurality of conductive bond pads contacts the second plurality of conductive bond pads and the first plurality of shield structures contacts the second plurality of shield structures at the bonding interface.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240304259
    Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.
    Type: Application
    Filed: April 10, 2023
    Publication date: September 12, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Po-Hao Chen, Yu-Cheng Hsu, Wei Lin
  • Publication number: 20240304235
    Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.
    Type: Application
    Filed: April 17, 2023
    Publication date: September 12, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Hao Chen, Po-Cheng Su, Shih-Jia Zeng, Yu-Cheng Hsu, Wei Lin
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Publication number: 20240297120
    Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a bridge structure, and a plurality of conductive bumps. The first semiconductor die and the second semiconductor die are disposed over the first redistribution layer. The bridge structure is disposed under the first redistribution layer. The first semiconductor die is electrically coupled to the second semiconductor die through the first redistribution layer and the bridge structure. The conductive bumps are disposed under the first redistribution layer and are coupled to the first redistribution layer. The bridge structure is disposed between at least two of the conductive bumps.
    Type: Application
    Filed: January 9, 2024
    Publication date: September 5, 2024
    Inventors: Wei-Yu CHEN, Yi-Lin TSAI, Nai-Wei LIU, Shih-Chin LIN, Wen-Sung HSU
  • Patent number: 12063792
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: August 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 11760190
    Abstract: An electric vehicle cooling system includes a vehicle control unit (VCU), a coolant pump controller, a motor controller, a motor, a vehicle charger, an electronic coolant pump, and a cooling plate. The electronic coolant pump, the vehicle charger, the motor controller, the motor, and the cooling plate are connected in sequence to form a closed coolant loop for a coolant. Either the VCU or the coolant pump controller of the electronic coolant pump can control the electronic coolant pump to switch between an idle mode and a normal mode according to a coolant temperature detected from the closed coolant loop. Under the normal mode, the VCU controls the electronic coolant pump to have an ideal pumping speed according to the coolant temperature detected from the closed coolant loop and a rotational speed of the motor, ensuring good cooling efficiency.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 19, 2023
    Assignee: Kwang Yang Motor Co., Ltd.
    Inventors: Wei-Lin Hsu, Min-Tse Hsu
  • Patent number: 11730915
    Abstract: The present disclosure provides an image display method and an image display system for alleviating motion sickness. The image display method includes: obtaining a number of shock and speed information of a transportation; comparing at least one of the shock and speed information with one or more than one corresponding threshold to determine whether motion sickness occurs; and in response to the determination that motion sickness occurs, positioning a position of a first image displayed on a display unit according to the shock and speed information.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: August 22, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Lin Hsu, Hong-Ming Dai
  • Patent number: 11621613
    Abstract: The present invention relates to an electric motor and an electric tool equipped with the electric motor. The electric motor includes a rotor, a stator, a coil module wound around the stator, a Hall unit and a wiring circuit unit. The Hall unit includes a Hall circuit board disposed around a rotating shaft of the rotor, and a Hall module for sensing rotation of the rotor. The wiring circuit unit is independent of the Hall circuit board and includes a three-phase power source interface. The wiring circuit unit electrically connects coils of the coil module to the power source interfaces respectively by groups. By separately disposing the Hall unit and the wiring circuit unit independently, a volume of the Hall circuit board can be reduced, and an area blocking an airflow path of a heat dissipation unit can be reduced, so heat dissipation effect of the electric motor and the electric tool can be improved.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 4, 2023
    Assignee: TECHWAY INDUSTRIAL CO., LTD.
    Inventors: Fu-Hsiang Chung, Hong Fang Chen, Wei-Ting Chen, Wei-Lin Hsu
  • Publication number: 20220160993
    Abstract: The present disclosure provides an image display method and an image display system for alleviating motion sickness. The image display method includes: obtaining a number of shock and speed information of a transportation; comparing at least one of the shock and speed information with one or more than one corresponding threshold to determine whether motion sickness occurs; and in response to the determination that motion sickness occurs, positioning a position of a first image displayed on a display unit according to the shock and speed information.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 26, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Lin HSU, Hong-Ming DAI
  • Patent number: 11313523
    Abstract: A light-emitting diode (LED) net light includes a plurality of electrical lines and a plurality of LEDs. Each of the plurality of LEDs is connected across two adjacent electrical lines without breaking the plurality of electrical lines. The plurality of LEDs connected to the same electrical line are mutually spaced, and the plurality of LEDs in the same row are respectively connected to two different electrical lines and are mutually spaced. In the LED net light, the plurality of LEDs are directly connected by plurality of the electrical lines, such that the plurality of LEDs serve as nodes to enable the plurality of electrical lines to stretch into a net structure. Accordingly, the invention does not use those supporting lines, but forms a net structure by having each of the plurality of LEDs be connected across two adjacent electrical lines.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 26, 2022
    Inventor: Wei-Lin Hsu
  • Publication number: 20220111722
    Abstract: An electric vehicle cooling system includes a vehicle control unit (VCU), a coolant pump controller, a motor controller, a motor, a vehicle charger, an electronic coolant pump, and a cooling plate. The electronic coolant pump, the vehicle charger, the motor controller, the motor, and the cooling plate are connected in sequence to form a closed coolant loop for a coolant. Either the VCU or the coolant pump controller of the electronic coolant pump can control the electronic coolant pump to switch between an idle mode and a normal mode according to a coolant temperature detected from the closed coolant loop. Under the normal mode, the VCU controls the electronic coolant pump to have an ideal pumping speed according to the coolant temperature detected from the closed coolant loop and a rotational speed of the motor, ensuring good cooling efficiency.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 14, 2022
    Applicant: Kwang Yang Motor Co., Ltd.
    Inventors: Wei-Lin HSU, Min-Tse HSU
  • Patent number: 11242106
    Abstract: An electric bike having an improved effect of heat dissipation has a body, a driving device, and a battery. The body has a frame, a rear wheel, and a front wheel, wherein the rear wheel and the front wheel are mounted to the frame. The driving device is mounted to the body and has a motor and a shell. The motor is connected with the frame and has a front end near the front wheel and a rear end near the rear wheel. The shell covers the motor and has multiple inlets and multiple outlets disposed therethrough. The multiple inlets are located near the front end of the motor. The multiple outlets are located near the rear end of the motor. The battery is electrically connected to the motor. The front wheel, the battery, the motor, and the rear wheel are serially aligned.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 8, 2022
    Assignee: TECHWAY INDUSTRIAL CO., LTD.
    Inventors: Hong-Fang Chen, Wei-Ting Chen, Wei-Lin Hsu, Ju-Sheng Cheng, Teng-Mao Hong