Abstract: The present disclosure provides a low-light solar boost converter and a control method therefore. The control method comprises the boost converter starting to operate in a PWM mode; determining whether the voltage of the input terminal is larger than a reference input voltage, the boost converter operating in the PWM mode when the voltage of the input terminal is larger than the reference input voltage, otherwise the boost converter operating in a burst mode, wherein a burst time period of the burst mode increases when the voltage of the input terminal decreases; during the burst mode determining whether the voltage of the output terminal is less than a first preset output voltage, the boost converter operating in the PWM mode when the voltage of the output terminal is less than the first preset output voltage, otherwise the boost converter operating in the burst mode.

Abstract: A positioner and a probe head of a probe card are provided. The positioner has a main opening, a first sub-opening, a second sub-opening, a third sub-opening, a fourth sub-opening, a first positioning portion, a second positioning portion, a first elastic portion and a second elastic portion. The first sub-opening, the second sub-opening, the third sub-opening, and the fourth sub-opening are sequentially arranged at the periphery of the main opening and are communicated to the main opening. A stiffness of the first positioning portion and a stiffness of the second positioning portion are higher than a stiffness of the first elastic portion and a stiffness of the second elastic portion.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract: A detecting system for detecting an under-test light of an under-test object includes a light spatial distribution unit, a chromatic-dispersion light-splitting unit and a detecting unit. The light spatial distribution unit is disposed on a side of the under-test object to receive the under-test light and form a plurality of point light sources. The chromatic-dispersion light-splitting unit is disposed on a side of the light spatial distribution unit to receive the point light sources and produce a light-splitting signal. The detecting unit is disposed on a side of the chromatic-dispersion light-splitting unit to receive the light-splitting signal and produce an optical field distribution of the under-test light.

Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.

Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

Abstract: An oscillation structure of micro actuator is described. In the oscillation structure, a pair of torsion bars is disposed along a first axis perpendicular to a second axis. The first frame is connected to the pair of torsion bars wherein the torsion bars are disposed on the outer periphery of a first frame along the first axis and a second frame is disposed inside the first frame. Each of the first connection members connects the first frame to the second frame therebetween, and each of the second connection members connects the second frame to the oscillation body therebetween such that the first frame, the second frame and the oscillation body are allowed to rotate about the first axis by the torsion bars as a structure assemblies at an identical angle. The oscillation structure effectively reduces the dynamic deformation of micro actuator.

Abstract: A mating connector includes a plastic body, a first terminal group and a second terminal group received in the plastic body, a retaining elastic sheet retained at the plastic body and located at a side of the first terminal group and the second terminal group, a middle shielding sheet located between the first terminal group and the second terminal group, and a shielding case contacting the middle shielding sheet. An urging portion is extended from the middle shielding sheet and abuts the retaining elastic sheet. The middle shielding sheet shields an interference signal between plate surfaces of the first and second terminal groups. The retaining elastic sheet shields an interference signal between side surfaces of the first and second terminal groups.

Abstract: A system includes a processing node configured to send authorized inbound messages to registered enterprise networks. An authorized message is a message that includes trusted source indicia. Trusted source indicia indicates that the message was sent by one or more of the processing node or an authenticated message transfer node associated with one of the registered enterprise networks. The system may further include an administration node configured to maintain registration of a plurality of message transfer nodes associated with the enterprise networks. A method includes receiving outbound messages from an authenticated message transfer node of an enterprise network, screening the messages for threats to determine whether to send the messages to associated recipients, applying a first message identifier to each message, wherein the first message identifier can be used to track the message and, for each message, sending the message to the associated recipient if no threats are detected in the message.

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract: A method for generating a circuit design of an integrated circuit, the circuit design comprising a functional area (FA) and a non-functional area is provided. The method comprises the steps of providing a description of a test cell (TC) to an electronic design automation (EDA) tool and inserting the test cell (TC) into the circuit design. Therein, the description of the test cell (TC) comprises a description of a test structure (HS) and the test structure (HS) is designed to be sensitive to variations of a manufacturing process. Furthermore, the test cell (TC) is inserted into a non-functional area and the inserting is performed automatically by the EDA tool. The test structure (HS) is intentionally designed to be sensitive to variations of the manufacturing process, in contrast to regular structures within the circuit description.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Abstract: Systems and methods are provided for allowing subscriber message sending profiles to be maintained and used in conjunction with behavior-based anomaly detection techniques and traditional content-based spam signature filtering to enable application of appropriate message disposition policies to outbound subscriber message traffic. According to one embodiment, subscriber profiles are constructed for multiple subscriber accounts associated with a service provider based on outbound message flow originated from the subscriber accounts. Then, possible subscriber account misuse may be discovered by performing behavior-based anomaly detection, including a comparison of a subscriber profile associated with the subscriber account with recent subscriber account usage information, to identify one or more behavioral anomalies in outbound message flow originated from a subscriber account, the behavior-based anomaly detection.

Abstract: A locking assembly used to lock at least one electronic device in a communication apparatus includes a housing, a latching member, a spring member and a key member. The latching member is pivotably connected to the housing by a pivoting member, and includes a pair of latching portions used to pass through the housing to be locked in the communication apparatus. The spring member is elastically connected between the housing and the latching member. The key member includes a pair of coupling portions used to be inserted into the housing and engage with the pair of receiving portions to make the latching member rotate relative to the housing about the pivoting member, so as to make the pair of latching portions to be released from the corresponding latching holes.

Abstract: A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.

Abstract: Pharmaceutical composition comprising antibodies or antigen binding fragments thereof that bind to SSEA-4 are disclosed herein, as well as methods of use thereof. Methods of use include, without limitation, cancer therapies and diagnostics. The antibodies of the disclosure can bind to certain cancer cell surfaces. Exemplary targets of the antibodies disclosed herein can include carcinomas, such as those in brain, lung, breast, mouse, esophagus, stomach, liver, bile duct, pancreas, colon, kidney, cervix, ovary, and/or prostate cancer.

Abstract: The present invention provides compounds of formula I: or a pharmaceutically acceptable salt, tautomer, or stereoisomer, thereof, wherein the variables are as defined herein. The present invention further provides pharmaceutical compositions comprising such compounds and methods of using such compounds for treating, preventing, inhibiting, ameliorating, or eradicating the pathology and/or symptomology of a disease caused by a Plasmodium parasite, such as malaria.