Abstract: An electronic device includes a housing defining an internal volume, a front opening, and a rear opening. The electronic device can include a display component disposed at the front opening and a rear cover disposed at the rear opening. A logic board can be disposed in the internal volume. The device can also include a thin film thermopile including a cold junction bonded to the logic board and a hot junction bonded to the rear cover.

Abstract: An electronic device has sensors. More particularly, the electronic device is a small form factor electronic device such as earbuds, styluses, or electronic pencils, earphones, and so on. In some implementations, one or more touch sensors and one or more force sensors are coupled to a flexible circuit. In various implementations, the touch sensor and the force sensor are part of a single module controlled by a single controller. In a number of implementations, the flexible circuit is laminated to one or more portions of an interior surface of the electronic device.

Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.

Abstract: The present invention provides a wireless communication method of an electronic device, wherein the electronic device includes a first radio and a second radio, a maximum bandwidth or a maximum. NSS supported by the first radio is different from a maximum bandwidth or a maximum NSS supported by the second radio. The wireless communication method includes the step of: using the first radio to communicate with another electronic device; determining if parameters of the electronic device satisfy a condition; and in response to the parameters of the electronic device satisfying the condition, enabling the second radio and using the second radio to communicate with the another electronic device, and disabling the first radio.

Abstract: An electronic device includes a chassis casing, a device casing, a latch assembly, a bracket, and a rotating shaft assembly. The chassis casing includes a bottom plate. The device casing is detachably disposed in the chassis casing, and the device casing is provided with a stopper. The latch assembly is disposed at the chassis casing, and the latch assembly includes a sliding member. The bracket is disposed in the chassis casing and at an end of the device casing opposite to the latch assembly. The rotating shaft assembly is respectively connected to the device casing and the bracket. The device casing is adjustable between an installation position and an lifting position via the rotating shaft assembly. The sliding member of the latch assembly is used to fix the stopper, so that the device casing is located at the installation position.

Abstract: The present disclosure provides a positioning method, including: obtaining a current local topology map established based on objects in an environment currently observed by a robot, obtaining a full topology map pre-established based on objects in a full environment in a preset area, the current local topology map and the full topology map including nodes representing the objects; matching a node pair to be associated constructed by two nodes in the current local topology map and two nodes in the full topology map; if a degree of association of the node pair to be associated is greater than a threshold, determining that the node pair to be associated is an associated node pair; and determining a pose of the robot according to one of a plurality of search ranches, with a largest number of associated node pairs.

Abstract: An integrated driving device is provided. The integrated driving device includes a touch sensing circuit and an optical sensing circuit. The touch sensing circuit is configured to perform touch sensing in a plurality of touch sensing periods during a first frame period. The optical sensing circuit is configured to perform optical sensing during at least one optical sensing period during the first frame period to obtain optical sensing signals for generating first ambient light information. The touch sensing periods and the optical sensing period are non-overlapping. Correspondingly, an operation method of an integrated driving device is also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.

Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.

Abstract: The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.

Abstract: The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth in a lower level of the CFET, adding a contact material to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot of the unfinished CFET structure, adding a conductive material within a vertical channel, the conductive material being in contact with the added contact material and the BPR to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.