Abstract: A method and device for converting an input light signal into an output light signal, in an optical component is described. An input light signal, at a first wavelength, and a first light beam which may be at a second wavelength, are received at the component. The input light signal and the first light beam interfere in the component to form an interference pattern, which modifies a reflectivity spectrum of the component to increase the reflectivity of the component in a portion of the reflectivity spectrum. A second light beam, having a second wavelength corresponding with a wavelength within the portion of the reflectivity spectrum, is also received at the component and is then reflected from the component, in dependence upon the portion of the reflectivity spectrum, to generate the output light signal at the second wavelength. This enables conversion of light signals to signals at a different wavelength.

Abstract: A method and device for converting an input light signal into an output light signal, in an optical component is described. An input light signal, at a first wavelength, and a first light beam which may be at a second wavelength, are received at the component. The input light signal and the first light beam interfere in the component to form an interference pattern, which modifies a reflectivity spectrum of the component to increase the reflectivity of the component in a portion of the reflectivity spectrum. A second light beam, having a second wavelength corresponding with a wavelength within the portion of the reflectivity spectrum, is also received at the component and is then reflected from the component, in dependence upon the portion of the reflectivity spectrum, to generate the output light signal at the second wavelength. This enables conversion of light signals to signals at a different wavelength.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: An apparatus having and method of forming grooves in the surface of a substrate adjacent and parallel to sidewall locations for circuit chips or die mounted on the surface. The grooves have physical dimensions to retain fill material formed between the packages and the surface of the substrate so that the fill material does not bridge between chips, thus reducing warping of the substrate due to mismatches in coefficient of thermal expansion (CTE) between the fill material, the substrate, the chips, and mold material formed over the substrate, under fill, and chips.