Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.

Abstract: Various embodiments of the teachings herein include an image processing system comprising: a video stream processing device configured to receive a video stream, segment the video stream into multiple frames of pictures arranged in chronological order, and distribute the multiple frames of pictures to edge computing devices in a connected edge computing device group; and a picture collecting device configured to receive pictures from the edge computing device group. The individual edge computing devices in the edge computing device group are each configured to subject the received pictures to target identification, and send the pictures marked with a region in which an identified target is located. The picture collecting device is further configured to restore in chronological order as a video stream the received pictures marked with target identification results.

Abstract: Various embodiments include a method for product quality inspection on a group of products. The method may include: getting for each product in the group of products: image, value for each known fabrication parameter affecting quality of the group of products, and quality evaluation result; training a neural network. A layer of the neural network comprises at least one first neuron and at least one second neuron; each first neuron represents a known fabrication parameter affecting quality of the group of products and each second neuron represents an unknown fabrication parameter affecting quality of the group of products; and the images of the group of products are input to the neural network, the quality evaluation results are output of the neural network, and the value of each first neuron is set to the value for the known fabrication parameter the first neuron representing.

Abstract: Various embodiments include a method for product quality inspection on a group of products. The method may include: getting for each product in the group of products: image, value for each known fabrication parameter affecting quality of the group of products, and quality evaluation result; training a neural network. A layer of the neural network comprises at least one first neuron and at least one second neuron; each first neuron represents a known fabrication parameter affecting quality of the group of products and each second neuron represents an unknown fabrication parameter affecting quality of the group of products; and the images of the group of products are input to the neural network, the quality evaluation results are output of the neural network, and the value of each first neuron is set to the value for the known fabrication parameter the first neuron representing.

Abstract: Various embodiments include a method for labeling a data point comprising executing a labeling operation on a target data set, wherein the target data set comprises a plurality of data points, each data point representing a service instance. The labeling operation comprises dividing the target data into subsets. For each subset, then: receiving input designating a mark for a first data point, illustrating the situation of the service instance represented by the data point; determining whether the similarity between the mark and a mark previously designated for a second data point in the target data set satisfies a preset condition; if the condition is not satisfied, taking the first subset as a target data set to re-execute the labeling operation; and if the condition is satisfied, setting, for each data point, a mark associated with the mark previously designated for a data point in the target data set.

Abstract: A method of reducing the dimension of an imprint structure on a substrate, the method comprising the steps of: (a) providing a substrate having at least one imprint structure thereon, said structure being formed of an inorganic-organic compound comprising an inorganic moiety and a polymer moiety, said polymer moiety having a lower vaporization temperature than the melting point of said inorganic moiety; and (b) selectively removing at least part of the polymer moiety while enabling at least part of the inorganic moiety to form a substantially continuous inorganic phase in said imprint structure, wherein the removal of the at least part of the polymer moiety from the imprint structure reduces the dimension of the imprint structure.

Abstract: A method and device for converting an input light signal into an output light signal, in an optical component is described. An input light signal, at a first wavelength, and a first light beam which may be at a second wavelength, are received at the component. The input light signal and the first light beam interfere in the component to form an interference pattern, which modifies a reflectivity spectrum of the component to increase the reflectivity of the component in a portion of the reflectivity spectrum. A second light beam, having a second wavelength corresponding with a wavelength within the portion of the reflectivity spectrum, is also received at the component and is then reflected from the component, in dependence upon the portion of the reflectivity spectrum, to generate the output light signal at the second wavelength. This enables conversion of light signals to signals at a different wavelength.

Abstract: A method and device for converting an input light signal into an output light signal, in an optical component is described. An input light signal, at a first wavelength, and a first light beam which may be at a second wavelength, are received at the component. The input light signal and the first light beam interfere in the component to form an interference pattern, which modifies a reflectivity spectrum of the component to increase the reflectivity of the component in a portion of the reflectivity spectrum. A second light beam, having a second wavelength corresponding with a wavelength within the portion of the reflectivity spectrum, is also received at the component and is then reflected from the component, in dependence upon the portion of the reflectivity spectrum, to generate the output light signal at the second wavelength. This enables conversion of light signals to signals at a different wavelength.

Abstract: A method of reducing the dimension of an imprint structure on a substrate, the method comprising the steps of: (a) providing a substrate having at least one imprint structure thereon, said structure being formed of an inorganic-organic compound comprising an inorganic moiety and a polymer moiety, said polymer moiety having a lower vaporization temperature than the melting point of said inorganic moiety; and (b) selectively removing at least part of the polymer moiety while enabling at least part of the inorganic moiety to form a substantially continuous inorganic phase in said imprint structure, wherein the removal of the at least part of the polymer moiety from the imprint structure reduces the dimension of the imprint structure.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: An apparatus having and method of forming grooves in the surface of a substrate adjacent and parallel to sidewall locations for circuit chips or die mounted on the surface. The grooves have physical dimensions to retain fill material formed between the packages and the surface of the substrate so that the fill material does not bridge between chips, thus reducing warping of the substrate due to mismatches in coefficient of thermal expansion (CTE) between the fill material, the substrate, the chips, and mold material formed over the substrate, under fill, and chips.