Abstract: Methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming a stack gate structure overlying a semiconductor substrate. The method forms a select gate material overlying the stack gate structure and the semiconductor substrate and having a planar surface overlying the stack gate structure. The method includes anisotropically etching the select gate material to define a select gate adjacent the stack gate structure, wherein the select gate is formed with a planar upper surface.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface.