Patents by Inventor Wei-Luen SUEN
Wei-Luen SUEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9355970Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: December 3, 2015Date of Patent: May 31, 2016Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Publication number: 20160086896Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Patent number: 9287417Abstract: Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.Type: GrantFiled: January 16, 2014Date of Patent: March 15, 2016Assignee: XINTEC INC.Inventors: Wei-Luen Suen, Shu-Ming Chang, Yu-Lung Huang, Yen-Shih Ho, Tsang-Yu Liu
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Patent number: 9209124Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: GrantFiled: August 12, 2013Date of Patent: December 8, 2015Assignee: XINTEC INC.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 9165890Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.Type: GrantFiled: July 15, 2013Date of Patent: October 20, 2015Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Shih-Chin Chen, Yi-Ming Chang, Chien-Hui Chen, Chia-Ming Cheng, Wei-Luen Suen, Chen-Han Chiang
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Publication number: 20150179831Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Inventors: Wei-Luen SUEN, Wei-Ming CHIEN, Po-Han LEE, Tsang-Yu LIU, Yen-Shih HO
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Publication number: 20150097286Abstract: A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate.Type: ApplicationFiled: December 11, 2014Publication date: April 9, 2015Inventors: Wei-Luen SUEN, Chia-Sheng LIN, Yen-Shih HO, Tsang-Yu LIU
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Patent number: 8963312Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.Type: GrantFiled: July 23, 2014Date of Patent: February 24, 2015Assignee: Xintec, Inc.Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Patent number: 8952501Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: GrantFiled: July 24, 2013Date of Patent: February 10, 2015Assignee: Xintec, Inc.Inventors: Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
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Publication number: 20140332968Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20140332969Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN, Chi-Chang LIAO
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Publication number: 20140332908Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN, Ho-Yin YIU
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Publication number: 20140332983Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventors: Yen-Shih HO, Tsang-Yu LIU, Shu-Ming CHANG, Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20140203387Abstract: Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.Type: ApplicationFiled: January 16, 2014Publication date: July 24, 2014Applicant: XINTEC INC.Inventors: Wei-Luen SUEN, Shu-Ming CHANG, Yu-Lung HUANG, Yen-Shih HO, Tsang-Yu LIU
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Publication number: 20140054786Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.Type: ApplicationFiled: August 12, 2013Publication date: February 27, 2014Applicant: XINTEC INC.Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN
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Publication number: 20140015111Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.Type: ApplicationFiled: July 15, 2013Publication date: January 16, 2014Inventors: Yen-Shih HO, Shih-Chin CHEN, Yi-Ming CHANG, Chien-Hui CHEN, Chia-Ming CHENG, Wei-Luen SUEN, Chen-Han CHIANG
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Publication number: 20130307125Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: XINTEC INC.Inventors: Yu-Lung HUANG, Chao-Yen LIN, Wei-Luen SUEN, Chien-Hui CHEN