Patents by Inventor Wei-Lun Cheng

Wei-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161672
    Abstract: An electronic circuit including a plurality of common terminals, a first circuit, a second circuit, and a plurality of switch units is provided. The first circuit is configured to output display driving signals to data lines of a display panel via the common terminals. The second circuit is configured to receive fingerprint sensing signals from fingerprint sensing lines of the display panel via the common terminals. Each of the switch units includes a first terminal coupled to one of the common terminals and a plurality of second terminals coupled to the first circuit and the second circuit. The switch units are grouped into a plurality of groups, and each group corresponds to a fingerprint sensing channel of the second circuit.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
  • Publication number: 20240153842
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11935452
    Abstract: An electronic circuit for operating with a display panel including touch sensors and fingerprint sensors is provided. The electronic circuit includes a first circuit, a second circuit, a third circuit, a first switch circuit and a control circuit. The first circuit generates display driving signals for driving the display panel. The second circuit receives fingerprint sensing signals from the fingerprint sensors. The third circuit determines a touch information according to touch sensing signals from the touch sensors. The first switch circuit includes a plurality of first switch units, each of the first switch units includes a first switch element and a second switch element. The control circuit controls the first switch circuit to transmit the display driving signals in a first time interval, controls the first switch circuit to transmit the fingerprint sensing signals in a second time interval, and controls the third circuit to receive the fingerprint sensing signals in a third time interval.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 19, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
  • Patent number: 11916110
    Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ching Wang, Wei-Yang Lee, Ming-Chang Wen, Jo-Tzu Hung, Wen-Hsing Hsieh, Kuan-Lun Cheng
  • Publication number: 20230380867
    Abstract: The invention provides a vaginal dilator including a spiral body and a control rod, wherein the spiral body includes a first surface, a second surface, a buckling edge, a fixing seat and a plurality of positioning seats. The buckling edge is adjacent to the first surface and the second surface. The fixing seat is arranged on a side of the first surface which is adjacent to the buckling edge. The plurality of positioning seats are separately arranged on an other side of the first surface opposite to the side provided with the fixing seat. The control rod includes a locking end locked on the fixing seat.
    Type: Application
    Filed: December 5, 2022
    Publication date: November 30, 2023
    Inventors: Wei-Lun CHENG, Ing-Luen SHYU, Chun-Pei CHIU
  • Patent number: 8237250
    Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 7, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Publication number: 20120119342
    Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 17, 2012
    Applicants: MediaTek Inc., ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng, Hsueh-Te Wang, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Ping-Feng Yang
  • Patent number: 8124447
    Abstract: The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: February 28, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Patent number: 8106492
    Abstract: The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: January 31, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Publication number: 20100258934
    Abstract: The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound.
    Type: Application
    Filed: August 31, 2009
    Publication date: October 14, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: PAO-HUEI CHANG CHIEN, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Publication number: 20100258920
    Abstract: The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability.
    Type: Application
    Filed: August 26, 2009
    Publication date: October 14, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Publication number: 20100258921
    Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound.
    Type: Application
    Filed: August 31, 2009
    Publication date: October 14, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: PAO-HUEI CHANG CHIEN, PING-CHENG HU, PO-SHING CHIANG, WEI-LUN CHENG
  • Publication number: 20100044843
    Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.
    Type: Application
    Filed: April 17, 2009
    Publication date: February 25, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Publication number: 20100044850
    Abstract: An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier.
    Type: Application
    Filed: March 16, 2009
    Publication date: February 25, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Hung Lin, Pao-Huei Chang Chien, Ping-Cheng Hu, Wei-Lun Cheng