Patents by Inventor Wei-Lun Jen
Wei-Lun Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113049Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.Type: ApplicationFiled: October 3, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Cemil S. Geyik, Kemal Aygun, Tarek A. Ibrahim, Wei-Lun Jen, Zhiguo Qian, Dilan Seneviratne
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Patent number: 11923307Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
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Publication number: 20230369192Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Jonathan ROSCH, Wei-Lun JEN, Cheng XU, Liwei CHENG, Andrew BROWN, Yikang DENG
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Patent number: 11769719Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.Type: GrantFiled: June 25, 2018Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Jonathan Rosch, Wei-Lun Jen, Cheng Xu, Liwei Cheng, Andrew Brown, Yikang Deng
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Patent number: 11764150Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.Type: GrantFiled: July 3, 2019Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Tarek Ibrahim, Wei-Lun Jen
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Patent number: 11521931Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie, Gang Duan, Kristof Kuwawi Darmawikarta, Wei-Lun Jen
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Patent number: 11270959Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.Type: GrantFiled: March 23, 2018Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Kirstof Darmawikarta, Srinivas Pietambaram, Prithwish Chatterjee, Sri Ranga Sai Boyapati, Wei Lun Jen
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Publication number: 20210391263Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
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Publication number: 20210391266Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie, Gang Duan, Kristof Kuwawi Darmawikarta, Wei-Lun Jen
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Publication number: 20210005550Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Inventors: Sri Chaitra Jyotsna CHAVALI, Tarek IBRAHIM, Wei-Lun JEN
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Solder resist layer structures for terminating de-featured components and methods of making the same
Patent number: 10658198Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.Type: GrantFiled: February 4, 2019Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling -
Publication number: 20200066830Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: Intel CorporationInventors: Krishna Bharath, Wei-Lun Jen, Huong Do, Amruthavalli Alur
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Publication number: 20190393143Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Inventors: Jonathan ROSCH, Wei-Lun JEN, Cheng XU, Liwei CHENG, Andrew BROWN, Yikang DENG
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Publication number: 20190295967Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Kirstof DARMAWIKARTA, Srinivas PIETAMBARAM, Prithwish CHATTERJEE, Sri Ranga Sai BOYAPATI, Wei Lun JEN
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SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME
Publication number: 20190181017Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.Type: ApplicationFiled: February 4, 2019Publication date: June 13, 2019Applicant: INTEL CORPORATIONInventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling -
Solder resist layer structures for terminating de-featured components and methods of making the same
Patent number: 10244632Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.Type: GrantFiled: March 2, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling -
SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME
Publication number: 20180255640Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.Type: ApplicationFiled: March 2, 2017Publication date: September 6, 2018Applicant: INTEL CORPORATIONInventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling