Abstract: A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm.

Abstract: The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a second adhesive material, at least one of the adhesive materials adapted to capturing debris. Methods are disclosed for making a vertically stacked semiconductor chip assemblies by joining first and second adhesive materials to form a laminated interposing layer between a first chip and second chip or substrate. In preferred embodiments of the invention, the interposing layer includes polyimide film and one adhesive material of relatively low elasticity, and another adhesive material having relatively high elasticity.