Abstract: A display panel and a pixel circuit thereof are provided. The pixel circuit includes a first transistor, a second transistor, a capacitor, a storage capacitor and a pixel capacitor. A first terminal of the first transistor is coupled to a source line, and a control terminal thereof is coupled to a gate line. A first terminal of the second transistor is coupled to a second terminal of the first transistor, and a control terminal of the second transistor is coupled to the gate line. A first terminal of the capacitor is coupled to the second terminal of the first transistor, and a second terminal of the capacitor receives a common voltage. The storage capacitor is coupled in series between a second terminal of the second transistor and the common voltage. The pixel capacitor is coupled in series between the second terminal of the second transistor and the common voltage.

Abstract: A display apparatus including scan lines, data lines, k clock signal lines and pixel groups is provided. k is an integer greater than 1. The pixel groups are respectively driven by the k clock signal lines, the data lines and their corresponding scan lines. Each pixel group includes pixel units respectively disposed at intersections of the corresponding scan lines and data lines. Each pixel unit includes a first switch, a second switch, a third switch, a fourth switch, a first pixel electrode and a second pixel electrode. The switches coupled to the common data line are driven by the scan lines in cooperation with the clock signal lines to reduce output signal lines of the driving circuit and a circuit layout area in favor of achieving a narrow-frame display apparatus and reduction in production cost of the display apparatus.

Abstract: A display device including scan lines, data lines, k clock signal lines and pixel groups is provided. The pixel groups are respectively driven by the data lines, the corresponding scan lines and the corresponding clock signal lines. Each pixel group includes pixel units respectively configured at intersections of the data lines and the corresponding scan lines, where the scan lines in each pixel group receive a same scan driving signal. Each pixel unit includes two switches and a pixel electrode. Conduction states of the two switches are respectively controlled by the corresponding scan line and the corresponding clock signal line, where clock signals of the clock signal lines corresponding to the pixel units on the adjacent scan lines have a phase difference of 1/k cycle.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display device including scan lines, data lines, k clock signal lines and pixel groups is provided. The pixel groups are respectively driven by the data lines, the corresponding scan lines and the corresponding clock signal lines. Each pixel group includes pixel units respectively configured at intersections of the data lines and the corresponding scan lines, where the scan lines in each pixel group receive a same scan driving signal. Each pixel unit includes two switches and a pixel electrode. Conduction states of the two switches are respectively controlled by the corresponding scan line and the corresponding clock signal line, where clock signals of the clock signal lines corresponding to the pixel units on the adjacent scan lines have a phase difference of 1/k cycle.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display apparatus including scan lines, data lines, k clock signal lines and pixel groups is provided. k is an integer greater than 1. The pixel groups are respectively driven by the k clock signal lines, the data lines and their corresponding scan lines. Each pixel group includes pixel units respectively disposed at intersections of the corresponding scan lines and data lines. Each pixel unit includes a first switch, a second switch, a third switch, a fourth switch, a first pixel electrode and a second pixel electrode. The switches coupled to the common data line are driven by the scan lines in cooperation with the clock signal lines to reduce output signal lines of the driving circuit and a circuit layout area in favor of achieving a narrow-frame display apparatus and reduction in production cost of the display apparatus.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal.

Abstract: A thin film transistor and a fabricating method thereof is provided. The thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a conductive pattern, a first electrode and a second electrode. The gate is disposed on a substrate. The gate insulation layer is disposed on the substrate to cover the gate. The semiconductor layer is disposed on the gate insulation layer. The conductive pattern, the first electrode and the second electrode are disposed on semiconductor layer. A first distance is formed between the first electrode and the second electrode, wherein the first electrode and the second electrode are a source and a drain. The conductive pattern is electrically connected to the first electrode, and a second distance smaller than the first distance is formed between the conductive pattern and the second electrode to define a channel.

Abstract: A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: An electrostatic discharge protection device for a liquid crystal display panel and a semiconductor structure thereof are disclosed. The semiconductor structure includes a gate electrode layer, a gate insulation layer, a semiconductor electrode layer, and a source/drain electrode layer. The gate electrode layer is disposed on a substrate and includes a taper. The gate insulation layer is disposed on the gate electrode layer and includes a first corner and a second corner. The semiconductor electrode layer is disposed on the gate insulation layer. The source/drain electrode layer is disposed on the semiconductor electrode layer. A first electrostatic discharge path and a second electrostatic discharge path are formed between the taper and the first and second corners.