Abstract: A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

Abstract: A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

Abstract: A level converting enable latch includes a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal, and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. The latch circuit sets a second data output signal in response to the first data output signal when a latch enable signal is set to a first logic value, and latches the second data output signal when the latch enable signal is set to a second logic value. The latch circuit includes a first control circuit. The first control circuit enables a latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.

Abstract: A level converting enable latch includes a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal, and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. The latch circuit sets a second data output signal in response to the first data output signal when a latch enable signal is set by a first logic value, and latches the second data output signal when the latch enable signal is set by a second logic value. The latch circuit includes a first control circuit. The first control circuit enables a latch feedback loop of the latch circuit when the latch enable signal is set by the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set by the first logic value.

Abstract: A stator assembly includes a stator core, an insulated wire frame, a coil, and an annular insulation structure. The stator core includes a magnetic yoke portion and a radial tooth portion, and the radial tooth portion extends from the magnetic yoke portion. The insulated wire frame disposed outside the radial tooth portion of the stator core has a winding slot. The coil is wound in the winding slot of the insulated wire frame annularly. The annular insulation structure is formed by injection moulding and wraps an area where the coil is exposed out of the insulated wire frame, and the coil is packaged between the insulated wire frame and the annular insulation structure.

Abstract: A stator assembly includes a stator core, an insulated wire frame, a coil, and an annular insulation structure. The stator core includes a magnetic yoke portion and a radial tooth portion, and the radial tooth portion extends from the magnetic yoke portion. The insulated wire frame disposed outside the radial tooth portion of the stator core has a winding slot. The coil is wound in the winding slot of the insulated wire frame annularly. The annular insulation structure is formed by injection moulding and wraps an area where the coil is exposed out of the insulated wire frame, and the coil is packaged between the insulated wire frame and the annular insulation structure.

Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.

Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.