Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit along an output axis. The transmission unit includes input-side and output-side cam discs having first and second grooved surfaces. The input unit includes an input disc having a plurality of first receiving grooves registered with the first grooved surfaces to receive input rollers, and an eccentric shaft rotated to drive rotation of the transmission unit in an eccentric cam motion. The output unit includes an output disc having an inner peripheral wall which engages with the output-side cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive output rollers. An outer diameter of each first toothed surface and an outer diameter of each second toothed surface is gradually increased along a direction parallel to the output axis.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: A selecting method of a non-simplified region of a 3D model of a multilayer metal circuit structure is used for selecting a first non-simplified region in a complete 3D model of a layout design of a multilayer metal circuit structure. The complete 3D model contains multiple layout layers. The electing method of the first non-simplified region includes at least one of first to fourth selecting modes. Through the selecting method of the non-simplified region of the present invention, the entire complete 3D can be effectively simplified in a programmed manner, shortening the overall electrical simulation time.

Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.