Abstract: A method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A guiding grid is disclosed and includes plural circumferential elements and plural radial elements. The circumferential elements are disposed concentrically relative to a central axis, spaced apart from each other in a radial direction, and form different heights relative to a bottom surface. One of the circumferential elements forms a top height relative to the bottom surface, so that the circumferential elements are divided into an outer-ring region and a central region in the radial direction. The circumferential elements located in the central region are increased in height relative to the bottom surface along the radial direction. The circumferential element located in the outer ring region are reduced in height relative to the bottom surface along the radial direction. The radial elements are connected between each of two adjacent circumferential elements. At least one of the radial elements is misaligned and discontinuous in the radial direction.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: An acceleration/deceleration control method of a CNC machine tool includes receiving an acceleration/deceleration timing signal and a velocity signal. The acceleration/deceleration timing signal is calculated to acquire a plurality of different first weight values and different second weight values by a first formula and a second formula. A velocity variation of the velocity signal is determined to be zero, positive or negative. The velocity signal is acquired, if the velocity variation is zero. A plurality of acceleration signals are acquired by the velocity signal multiplying each of the first weight values, if the velocity variable is positive. A plurality of deceleration signals are acquired by the velocity signal multiplying each of the second weight values, if the velocity variation is negative. The velocity signal, the acceleration signal and the deceleration signal are converted into a first driving signal, a second driving signal and a third driving signal.

Abstract: An acceleration/deceleration control method of a CNC machine tool includes receiving an acceleration/deceleration timing signal and a velocity signal. The acceleration/deceleration timing signal is calculated to acquire a plurality of different first weight values and different second weight values by a first formula and a second formula. A velocity variation of the velocity signal is determined to be zero, positive or negative. The velocity signal is acquired, if the velocity variation is zero. A plurality of acceleration signals are acquired by the velocity signal multiplying each of the first weight values, if the velocity variable is positive. A plurality of deceleration signals are acquired by the velocity signal multiplying each of the second weight values, if the velocity variation is negative. The velocity signal, the acceleration signal and the deceleration signal are converted into a first driving signal, a second driving signal and a third driving signal.