Patents by Inventor Wei-Ming Huang
Wei-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145255Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Ker-Yih KAO, Chin-Ming HUANG, Wei-Yuan CHENG, Jui-Jen YUEH, Kuan-Feng LEE
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Publication number: 20240112707Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.Type: ApplicationFiled: December 15, 2023Publication date: April 4, 2024Applicant: Etron Technology, IncInventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
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Patent number: 11944935Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.Type: GrantFiled: December 2, 2020Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Tsung-I Lin
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Patent number: 11944412Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.Type: GrantFiled: June 2, 2021Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
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Patent number: 11937903Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.Type: GrantFiled: December 29, 2020Date of Patent: March 26, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Chin-Wen Hsieh
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Patent number: 11917230Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.Type: GrantFiled: October 6, 2021Date of Patent: February 27, 2024Assignee: Quanta Cloud Technology Inc.Inventors: Yi-Neng Zeng, Keng-Cheng Liu, Wei-Ming Huang, Shih-Hsun Lai, Ji-Jeng Lin, Chia-Jui Lee, Liao Jin Xiang
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Patent number: 11894098Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.Type: GrantFiled: March 25, 2021Date of Patent: February 6, 2024Assignee: Etron Technology, Inc.Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
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Patent number: 11723495Abstract: Systems, methods and apparatus for dispensing of paper products. A dispenser comprising a housing comprising a product holding area defined by a front, back and two sides, and a dispenser throat defining an opening through the housing; a motor coupled to the rolled product and configured to rotate the rolled product in first and second directions; and a feed mechanism having a first side opening and a second side opening different from the first side opening, wherein both the first side and second side openings are different from that dispenser throat, and wherein the first side opening is configured to accept the tail when the rolled product has a first orientation and is rotated in the first direction and the second side opening is configured to accept the tail when the rolled product has a second orientation and is rotated in the second direction.Type: GrantFiled: March 29, 2019Date of Patent: August 15, 2023Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Richard P. Lewis, I-Chung Hou, Wan-Chih Lin, Ming-Chung Chung, Chih-An Chen, Wan-Chang Liang, Chan-Hao Chen, Huang-Keng Chen, Ching-Lung Mao, Wei-Ming Huang
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Publication number: 20230142132Abstract: A method for establishing a variation model related to circuit characteristics for performing circuit simulation includes: performing first, second, third, and fourth Monte Carlo simulation operations according to a first netlist file and predetermined process model data to generate a first, a second, a third, and a fourth performance simulation results, respectively, where the first netlist file is arranged to indicate a basic circuit in a circuit system; and execute a performance simulation results expansion procedure according to the first, the second, the third, and the fourth performance simulation results to generate a plurality of performance simulation results to establish the variation model, for performing the circuit simulation to generate at least one circuit simulation result according to one or more performance simulation results among the plurality of performance simulation results, where the number of the plurality of performance simulation results is greater than four.Type: ApplicationFiled: March 13, 2022Publication date: May 11, 2023Applicant: Realtek Semiconductor Corp.Inventors: Wei-Ming Huang, Szu-Ying Huang, Mei-Li Yu, Yu-Lan Lo
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Publication number: 20220201555Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.Type: ApplicationFiled: October 6, 2021Publication date: June 23, 2022Inventors: Yi-Neng Zeng, Keng-Cheng LIU, Wei-Ming HUANG, Shih-Hsun LAI, Ji-Jeng LIN, Chia-Jui LEE, Liao Jin Xiang
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Publication number: 20220192439Abstract: Systems, methods and apparatus for dispensing of paper products. A dispenser comprising a housing comprising a product holding area defined by a front, back and two sides, and a dispenser throat defining an opening through the housing; a motor coupled to the rolled product and configured to rotate the rolled product in first and second directions; and a feed mechanism having a first side opening and a second side opening different from the first side opening, wherein both the first side and second side openings are different from that dispenser throat, and wherein the first side opening is configured to accept the tail when the rolled product has a first orientation and is rotated in the first direction and the second side opening is configured to accept the tail when the rolled product has a second orientation and is rotated in the second direction.Type: ApplicationFiled: March 29, 2019Publication date: June 23, 2022Inventors: Richard P. Lewis, I-Chung Hou, Wan-Chih Lin, Ming-Chung Chung, Chih-An Chen, Wan-Chang Liang, Chan-Hao Chen, Huang-Keng Chen, Ching-Lung Mao, Wei-Ming Huang
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Publication number: 20220067323Abstract: A sensing device substrate includes a substrate and a sensing device. The sensing device is disposed on the substrate and includes a first electrode, a second electrode, a sensing layer, a conductive layer, and a first insulating layer. The first electrode is located on the substrate. The second electrode is overlapped with the first electrode. The sensing layer is located between the second electrode and the first electrode. The conductive layer is overlapped with the second electrode and electrically connected to the first electrode. The conductive layer has a first opening, and the first opening is overlapped with the sensing layer. The first insulating layer is located between the conductive layer and the second electrode. A display apparatus including the sensing device substrate is also provided.Type: ApplicationFiled: June 23, 2021Publication date: March 3, 2022Applicant: Au Optronics CorporationInventors: Ming-Yao Chen, Jui-Chi Lo, Wei-Ming Huang
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Patent number: 11143896Abstract: A touch display panel comprises a first substrate, a plurality of first sensing series and a plurality of second sensing series, wherein both the first sensing series and the second sensing series are above the first substrate, and the first sensing series and the second sensing series are crossly arranged to form a plurality of sensing series openings in between, a first insulating layer, covering the first sensing series and the second sensing series, a patterned black matrix layer, comprising a plurality of black matrix openings arranged in a matrix formation, a second insulating layer, covering the patterned black matrix layer; and a patterned common electrodes layer. The plurality of sensing series openings, the plurality of black matrix openings, and the patterned common electrode layer are overlapped.Type: GrantFiled: July 13, 2018Date of Patent: October 12, 2021Assignee: AU OPTRONICS CORP.Inventors: Tun-Chun Yang, Seok-Lyul Lee, Wei-Ming Huang
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Publication number: 20210217451Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.Type: ApplicationFiled: March 25, 2021Publication date: July 15, 2021Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
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Patent number: 10998017Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.Type: GrantFiled: October 4, 2018Date of Patent: May 4, 2021Assignee: Etron Technology, Inc.Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
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Publication number: 20190035440Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
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Publication number: 20180321773Abstract: A touch display panel comprises a first substrate, a plurality of first sensing series and a plurality of second sensing series, wherein both the first sensing series and the second sensing series are above the first substrate, and the first sensing series and the second sensing series are crossly arranged to form a plurality of sensing series openings in between, a first insulating layer, covering the first sensing series and the second sensing series, a patterned black matrix layer, comprising a plurality of black matrix openings arranged in a matrix formation, a second insulating layer, covering the patterned black matrix layer; and a patterned common electrodes layer. The plurality of sensing series openings, the plurality of black matrix openings, and the patterned common electrode layer are overlapped.Type: ApplicationFiled: July 13, 2018Publication date: November 8, 2018Inventors: Tun-Chun Yang, Seok-Lyul Lee, Wei-Ming Huang
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Patent number: 9423660Abstract: A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.Type: GrantFiled: March 9, 2015Date of Patent: August 23, 2016Assignee: Au Optronics CorporationInventors: Te-Chun Huang, Kuo-Yu Huang, Yu-Han Huang, Maw-Song Chen, Wei-Ming Huang