Abstract: An ultra-thin packaged component and its manufacturing method are provided. The packaged component includes a die, at least one conductive component, an encapsulant layer, and multiple conductive contacts. The encapsulant layer surrounds and covers the die and the conductive component, with multiple conductive contacts placed on the surface of the encapsulant layer that electrically connect the die and the conductive component. During the manufacturing of the packaged component, the die and the conductive component are first encapsulated with the encapsulant layer and then simultaneously thinned through grinding. Such process protects the die with the encapsulant layer to prevent cracking and reduces the thickness of the base layer of the die closer to that of its epitaxy layer, achieving the objective of thinness.

Abstract: A method of manufacturing pre-molded lead frame for packaging is disclosed. A first patterned aluminum metal layer is formed on a temporary carrier. A displacement reaction procedure is performed, in which at least part of the first patterned aluminum metal layer is replaced by copper metal so as to form a first copper metal wiring layer. A first molding compound is formed around the first copper metal wiring layer. The temporary carrier is removed.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: A semiconductor package with improved solderability at sidewall includes a chip, a molding compound encapsulating the chip, and multiple leads distributed at sidewalls of the semiconductor package. The leads are formed as a conductive layer that is electrically connected to bonding pads of the chip. Each of the leads has a stepped surface exposed from the molding compound, wherein the stepped surface is shaped by two sequentially overlapped photoresist layers. The stepped surface of each lead allows to accommodate more solder to enhance the reliability of a solder joint between the semiconductor and a printed circuit board. Therefore, the solder joints of the semiconductor package are easily inspected by automatic optical inspection (AOI) equipment.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.