Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Abstract: In accordance with at least one embodiment, a method, apparatus, and communication system provide intra-symbol multi-dimensional modulation (ISMM). A modulator can be provided modulate data according to ISMM for transmission.

Abstract: In accordance with at least one embodiment, a method, apparatus, and communication system provide intra-symbol multi-dimensional modulation (ISMM). A modulator can be provided modulate data according to ISMM for transmission.

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Abstract: A communication device includes a primary communication unit and an auxiliary communication unit. The primary communication unit is operable between an operational state in which a primary communication channel is able to be established for communication with a remote control station and a non-operational state in which the primary communication unit is unable to communicate with the remote control station and the auxiliary communication unit is configurable in an operational state for establishing an auxiliary communication channel for communicating with the remote control station. The primary and auxiliary communication channels include primary and auxiliary radio links respectively.

Abstract: A method for encoding a bit sequence is described comprising selecting a first coding block bit number and a first coding scheme; sub-dividing the bit sequence into at least one first bit block and a second bit block, wherein each of the at least one first bit block comprises the first coding block bit number of bits and the second bit block comprises less bits than the first coding block bit number; selecting a second coding scheme for the second bit block different from the first coding scheme; and encoding the at least one first bit block using the first coding scheme and encoding the second bit block using the second coding scheme.