Abstract: A method and related apparatus for storing program code and optimized power calibration (OPC) data in the same non-volatile memory is provided. The method is used for accessing OPC data from an optical discrecorder. The optical disc recorder is capable of obtaining OPC data of an optical disc by executing an optimized power calibrating process so as to record data onto the optical disc. The optical disc recorder has a first memory with a program code being stored therein and a second memory. The method includes registering the program code in the second memory, and writing the OPC data of the optical disc to the first memory according to the program code registered in the second memory.

Abstract: A digital signal processor (DSP) code download device is disclosed. The device is used for downloading a DSP code comprising a Servo system control code from a re-programmable memory and then storing the DSP code in a memory. The DSP code download device includes a re-programmable memory reader for downloading the DSP code from the re-programmable memory, a download procedure controller coupled to the re-programmable memory reader and a memory accessor coupled to the download procedure controller for accessing the memory. Accordingly, when the DSP code needs to be updated or corrected, it is only necessary to program the re-programmable memory with the required version of DSP code rather than to manufacture a new control chip.

Abstract: The invention discloses a signal decoding method for C3 decoding on a data storage medium. The data storage medium contains a lot of sectors, and each sector contains two C3 codes. Each C3 code contains a plurality of P codes and Q codes. The syndrome operation for an (N+1)th code and an error-correction for an N-th code are pipelined. An address for the (N+1)th code minus a predetermined value is an address for the N-th code.

Abstract: A multiplier for obtaining the product of elements in a Galois Field. The multiplier performs the multiplication of two n-bit elements, A(an-1, an-2, . . . , a3, a2, a1, a0) and B(bn-1, bn-2, . . . , b3, b2, b1, b0) in the Galois Field to yield the product C(cn-1, cn-2, . . . , c3, c2, c1, c0), wherein n≧1 ai(i=0˜n-1), bj(j=0˜n-1), and ck(k=O˜n-1) are all binary bits. The multiplier includes: an AND planer, for performing an AND logic operation of every bit ai in A(an-1, an-2, . . . , a3, a2, a1, a0) and every bit bj in B(bn-1, bn-2, . . . , b3, b2, b1, b0) to obtain (an-1bn-1, an-1bn-2, . . . , an-1b0, an-2bn-1, an-2bn-2, . . . , an-2b0, a0bn-1, a0bn-2, . . . , a0b0); and an XOR planer, for performing an XOR logic operation of the output from the AND planer to obtain C(cn-1, cn-2, . . . , c3, c2, c1, c0).

Abstract: A method and related apparatus for storing program code and optimized power calibration (OPC)data in the same non-volatile memory is provided. The method is used for accessing OPC data from an optical discrecorder. The optical disc recorder is capable of obtaining OPC data of an optical disc by executing an optimized power calibrating process so as to record data onto the optical disc. The optical disc recorder has a first memory with a program code being stored therein and a second memory. The method includes registering the program code in the second memory, and writing the OPC data of the optical disc to the first memory according to the program code registered in the second memory.

Abstract: A means and a method applied in syndrome generation in the Video/Audio processing system is disclosed. The syndromes thereof are effectively and rapidly generated simply using shift register and an exclusive or adder by a recursive operation. For the code words having a number of bytes, the syndromes can be generated by repeating exclusive or (XOR) operation between a shift bit and the above-mentioned bytes, without the extra step of table-matching, saving large memory capacity, greatly reducing the operation cycle and completing the operation rapidly.

Abstract: A system for updating a flash memory of a peripheral device including a host sending an update content. The host sends an update content. The peripheral device contains a peripheral interface controller and a flash memory. The peripheral interface controller couples to the host, and the flash memory couples to the peripheral interface controller. When the peripheral interface controller detects a signal for updating the flash memory from the host, the peripheral interface controller updates the flash memory according to the update content.

Abstract: A method for transferring data from a large capacity data storage device to a host machine. The method requires the attachment of a plurality of SRAM memory blocks to an optical disk reader. Each SRAM memory block is used as temporary storage area got a sector of data so that data can be proofread one sector at a time. As soon as the entire sector is checked and corrected, the error-free data is transferred to an external DRAM memory. Thereafter, correct data can be read from the DRAM by the host machine at any time. The internal SRAM memory serves as a buffer holding sectors of data so that error detection and error correction of individual sector can be carried out. Additionally, the external DRAM memory serves as a buffer holding the correct data for the host machine.

Abstract: A table matching method for multiplication of elements in Galois Field. First, a table of the byte value in Galois Field and the corresponding exponent is formed in the hardware. To perform the multiplication between two elements in the Galois Field, the corresponding exponents of the two elements are found out in advance. The two exponents are then added up to obtain a sum. Then, by using the table, a corresponding byte value of the sum can be obtained. The byte value is the product of the two elements in the Galois Field.

Abstract: A decoding device for deinterleaving data includes a write address generator, a read address generator, and a memory device. According to a method for deinterleaving data, the write address generator generates a write address according to parameters corresponding to the interleaving characteristics of an input signal. The write addresses are offset according to the parameters in order to apply a deinterleaving function to the input data. The read address generator generates a read address so as to sequentially read the stored data, to provide deinterleaved output data.