Patents by Inventor WEI-NAN FANG

WEI-NAN FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9490141
    Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Wei-Nan Fang, Jiann-Shiun Chen, Tzu-Yi Chuang
  • Publication number: 20160155649
    Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 2, 2016
    Inventors: WEI-NAN FANG, JIANN-SHIUN CHEN, TZU-YI CHUANG