Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

Abstract: A method of forming a semiconductor device includes providing a substrate having a recess, and growing an epitaxial feature in the recess. The method of growing the epitaxial feature includes: (a) growing a sub-layer of the epitaxial feature; (b) selectively etching the sub-layer of the epitaxial feature while providing a first UV radiation; and (c) repeating step (a) and step (b) alternately multiple times.

Abstract: An electronic device includes a substrate, a plurality of first retaining walls, a second retaining wall, and a light emitting element. The first retaining walls are arranged on the substrate. The second retaining wall is arranged on the substrate and disposed within one of the first retaining walls. The light emitting element is arranged on the substrate and disposed between the second retaining wall and one of the first retaining walls adjacent to the second retaining wall. In a cross section, there are a first distance between the light emitting element and the one of the first retaining walls, and a second distance between the light emitting element and the second retaining wall, wherein the second distance is smaller than the first distance.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

Abstract: A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.