Patents by Inventor Wei Pan

Wei Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200058632
    Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20200055859
    Abstract: Described herein are irreversible kinase inhibitor compounds, methods for synthesizing such irreversible inhibitors, and methods for using such irreversible inhibitors in the treatment of diseases. Further described herein are methods, assays and systems for determining an appropriate irreversible inhibitor of a protein, including a kinase.
    Type: Application
    Filed: March 22, 2019
    Publication date: February 20, 2020
    Inventors: Joseph J. Buggy, Wei Chen, Lee Honigberg, David J. Loury, Zhengying Pan, Erik J. Verner
  • Publication number: 20200053362
    Abstract: Techniques are disclosed for coding image data adaptively at different levels of downscaling. Such techniques may involve partitioning input data into pixel blocks for coding and performing content analysis on the pixel blocks. The pixel blocks may be input to block coders that operate at different pixel block sizes, which may code the pixel blocks input to them at their respective sizes. Except when a block coder operates at the partitioning size, block coders that operate at different pixel block sizes may perform downscaling of the pixel blocks to match their size with the block coders' respective coding size. A block decoder may invert the coding operations performed by the block coders, decoding coded image data at respective pixel block sizes, then upscaling decoded image data obtained therefrom to a common pixel block size. Image reconstruction may synthesize a resultant image from the decode pixel block data output by the decoders.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Xiang Fu, Linfeng Guo, Haiyan He, Wei Li, Xu Gang Zhao, Hao Pan, Xiaohua Yang, Krishnakanth Rapaka, Munehiro Nakazato, Haitao Guo
  • Publication number: 20200052171
    Abstract: A light emitting diode assembly structure includes a light emitting chip, a color converting layer, a light guiding member, and a reflecting member. The color converting layer coats the light emitting chip and the light guiding member coats the color converting layer. The planar or non-planar reflecting member is arranged over the light guiding member. The reflecting member faces toward the light emitting chip and changes the range of illumination of the light emitted by the light emitting chip. The reflecting member can be arranged on a side of the color converting layer and light can be irradiated towards the exterior of the light emitting diode assembly structure.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: ZHI-TING YE, SHYI-MING PAN, CHIH-WEI CHANG
  • Patent number: 10555433
    Abstract: A chassis includes a bottom plate, a fastener and a supporting component. The bottom plate includes a screw hole. The fastener comprises a threaded portion and a smooth portion that are connected to each other, and the threaded portion is configured to be screwed into the screw hole. The supporting component includes a through hole. The smooth portion of the fastener is configured to be disposed through the through hole so that the supporting component is rotatably disposed on the bottom plate so as to include a supporting position and a stored position. The supporting component is integrated.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 4, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chih-Wei Chiang, Yuan-Chang Yang, Shih-Wei Chen, Jeng-Ting Pan
  • Patent number: 10547437
    Abstract: The present invention relates to a synchronization signal transmitting device, method thereof and a power electronic apparatus with the device. The synchronization signal transmitting device comprises at least one serial differential signal transmitter for receiving an identical-period pulse signal and outputting a differential signal pair, at least one serial differential signal receiver for receiving the differential signal pair and outputting a single-ended signal, and at least one controller for receiving the single-ended signal. Moreover, the controller is configured for conducting a signal filtering process and/or a signal reconstruction process to the single-ended signal, so as to obtain a synchronization signal. Thus, the present invention shows the advantages of transmission and process purely by hardware without participation of software, without occupation to calculating ability of processors, high time accuracy, and low time delay.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: January 28, 2020
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Qielu Pan, Wei Guan, Hongyang Wu
  • Publication number: 20200007261
    Abstract: A radio-over-fiber communication beamforming device based on arrayed waveguide grating and a method thereof. The radio frequency signal is modulated onto a plurality of optical carriers of different wavelengths and processed by a programmable photonic true-time delay module in the optical domain. The programmable photonic true-time delay module includes optical switches and a plurality of cascaded AWGs which can provide different basic delays between adjacent wavelength channels. The basic delays of different stages of the AWG present a geometric sequence with a common ratio of 2. Optical carriers of different wavelengths enter different branches and undergo photoelectric conversion to obtain the radio frequency signals of different delays (phases) to realize a far-field beam directional radiation pattern.
    Type: Application
    Filed: December 18, 2017
    Publication date: January 2, 2020
    Applicant: SOUTHWEST JIAOTONG UNIVERSITY
    Inventors: Xihua ZOU, Peixuan LI, Wei PAN
  • Patent number: 10516030
    Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
  • Patent number: 10516050
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 24, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10516051
    Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Ching-Wei Tsai, Ying-Keung Leung, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 10510713
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 10510611
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 17, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Publication number: 20190378846
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Patent number: 10504236
    Abstract: A method of testing a battery includes causing a battery in a test environment to produce a fire having a flame that extends out from the battery, and capturing a digital image of a scene that includes at least a portion of a test environment and the flame, the digital image being formed using visible light. The method includes uploading the digital image to a computer configured to produce a quiver plot and identify points on the quiver plot that define a polygon that is an approximate outline of the flame. The computer is configured to determine dimensions of the polygon, and translate the dimensions from the quiver plot to the digital image, and from the digital image to dimensions of the flame in the scene. And the computer is configured to generate a displayable report that includes at least the dimensions of the flame.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 10, 2019
    Assignee: The Boeing Company
    Inventors: Elizabeth Killelea, Joseph Gonzalez, Jan Wei Pan
  • Patent number: 10505496
    Abstract: A method is provided for using asymmetrically focused photovoltaic conversion in a hybrid parabolic trough solar power system. Light rays received in a plurality of transverse planes are concentrated towards a primary linear focus in an axial plane, orthogonal to the transverse planes. T band wavelengths of light are transmitted to the primary linear focus, while R band wavelengths of light are reflected towards a secondary linear focus in the axial plane. The light received at the primary linear focus is translated into thermal energy. The light received at the secondary linear focus is asymmetrically focused along a plurality of tertiary linear foci, orthogonal to the axial plane. The focused light in each tertiary linear focus is concentrated into a plurality of receiving areas and translated into electrical energy. Asymmetrical optical elements are used having an optical input interfaces elongated along rotatable axes, orthogonal to the axial plane.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 10, 2019
    Assignee: DWP Energy Solutions, LLC
    Inventors: Brian Wheelwright, Wei Pan, Douglas Tweet
  • Patent number: 10504824
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20190370179
    Abstract: There are provided in the present disclosure a command forwarding method and device, a solar system, a central controller, and a computer-readable storage medium. The method includes: a receiving step of receiving a command; a storing step of storing a received command into a corresponding command storage area according to a priority; and a forwarding step of forwarding a command stored in the command storage area according to the priority.
    Type: Application
    Filed: September 20, 2018
    Publication date: December 5, 2019
    Inventors: Ya'nan XIAO, Wei PAN
  • Publication number: 20190372352
    Abstract: The present disclosure provides a method for controlling a solar energy system. The method includes: receiving component control information sent by an external control system, and executing a control operation corresponding to the component control information on a solar energy component connected to a junction box according to the component control information. A device for controlling a solar energy system, a central controller and a solar energy system are also provided.
    Type: Application
    Filed: September 20, 2018
    Publication date: December 5, 2019
    Inventors: Ya'nan XIAO, Wei PAN, Haifeng LI, Hongjie LI
  • Publication number: 20190348507
    Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Applicant: United Microelectronics Corp.
    Inventor: Chen-Wei Pan
  • Publication number: 20190340377
    Abstract: A data access method in a cloud computing environment is disclosed. The method may comprise, in a service object space of the cloud computing environment, receiving a request of a user for accessing a data package, the request including a user identification, determining a service object space of the data package corresponding to the request, and providing the data package to the user according to the service object space of the data package and the user identification.
    Type: Application
    Filed: July 12, 2019
    Publication date: November 7, 2019
    Inventors: Panfeng YUAN, Dong GUO, Wei ZHANG, Zihua PAN, Tingliang CHEN