Abstract: The subject application provides a portable electronic heating type device with an improved power converter topology configured for receiving a DC input voltage from the power supply and generate an AC output voltage to the heating element. The power converter is based on an inductor, a DC blocking capacitor and only one switching device. Heating power can be adjusted under a pulse-width-modulation mode, a fixed-on-time mode, a fixed-off-time mode or a frequency-modulation mode. The portable electronic heating type device has less switching loss and faster response. Therefore, it can be operated at higher frequency and more compact in size.

Abstract: Methods and systems for predicting successful data transmission during mass communications across computer networks featuring disparate entities and imbalanced data sets using machine learning models. For example, the methods and systems provide a prediction as to whether or not a communication will be successful prior to the transmission being sent. Moreover, in some embodiments, the methods and systems described herein provide probability of a successful transmission as a function of time. For example, the methods and system provide a probability of how likely a communication will succeed (or fail) if it is sent at various times. Additionally, in some embodiments, the methods and systems may alert a sender prior to the transmission of a communication that the transmission is likely to succeed or fail.

Abstract: Methods and systems for predicting successful data transmission during mass communications across computer networks featuring disparate entities and imbalanced data sets using machine learning models. For example, the methods and systems provide a prediction as to whether or not a communication will be successful prior to the transmission being sent. Moreover, in some embodiments, the methods and systems described herein provide probability of a successful transmission as a function of time. For example, the methods and system provide a probability of how likely a communication will succeed (or fail) if it is sent at various times. Additionally, in some embodiments, the methods and systems may alert a sender prior to the transmission of a communication that the transmission is likely to succeed or fail.

Abstract: The present invention discloses an electric cooker with fastening lock, comprising a heating base, a pot seated in the heating base and a lid for covering the pot, wherein handles are symmetrically arranged at opposite sides of outer wall of the heating base, and locking mechanisms, which can be locked to the handles by latches, are configured in both opposite edges on the upper surface of the lid; each locking mechanism comprises a locking base placed on the lid and a locking clip one end of which is hinged to the locking base, and each handle is provide with a locking hole for the insertion of another end of the locking clip and a pushing type switch for latching the another end of the lock clip when it was inserted in the locking hole.

Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

Abstract: A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.

Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.