Patents by Inventor Wei-Ping Lee

Wei-Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105505
    Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 11, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
  • Publication number: 20140312401
    Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.
    Type: Application
    Filed: September 12, 2013
    Publication date: October 23, 2014
    Applicant: INOTERA MEMORIES, INC.
    Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
  • Patent number: 6636548
    Abstract: A bottom electrode of a direct current electric arc furnace includes an electrode body extending through a hole defined in a bottom of the furnace. A circumferential flange is formed around a lower portion of the electrode body to which a ring connection member is attached. The connection member forms a ring channel defined by inner and outer walls from which inner and outer flanges radially extend in opposite directions. The inner flange is fixed to the circumferential flange of the electrode body by bolts. The outer flange is fixed to the furnace bottom for attaching the bottom electrode to the furnace bottom. The channel is located between the circumferential flange of the electrode body and an inside diameter of the hole defined in the furnace bottom for increasing radial distance between the electrode body and the hole of the furnace bottom. Insulative members are arranged on and under the circumferential flange of the electrode body for electrically isolating the electrode from the furnace bottom.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: October 21, 2003
    Assignee: Tung Ho Steel Enterprise Corporation
    Inventors: Lin-Her Leu, Wei-Ping Lee