Patents by Inventor Wei-ping Lu

Wei-ping Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190305115
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10340181
    Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10326005
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Patent number: 9334267
    Abstract: This invention provides compounds of Formula I: (Formula I should be inserted here) or a pharmaceutically acceptable salt thereof; pharmaceutical compositions comprising a compound of Formula I; and use of a compound of Formula I for treating specified cancers.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 10, 2016
    Assignee: Deciphera Pharmaceuticals, LLC
    Inventors: Daniel L. Flynn, Michael D. Kaufman, Lakshminarayana Vogeti, Scott Wise, Wei-Ping Lu, Bryan Smith, James R. Henry, Philip A. Hipskind, Sheng-Bin Peng
  • Patent number: 9187474
    Abstract: This invention provides compounds of Formula (I) or a pharmaceutically acceptable salt thereof; pharmaceutical compositions comprising a compound of Formula (I); and use of a compound of Formula (I) for treating specified cancers.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 17, 2015
    Assignees: Deciphera Pharmaceuticals, LLC, Eli Lilly and Company
    Inventors: Daniel L. Flynn, Michael D. Kaufman, Lakshminarayana Vogeti, Scott Wise, Wei-Ping Lu, Bryan Smith, Timothy Malcolm Caldwell, William C. Patt, James R. Henry, Philip A. Hipskind, Sheng-Bin Peng
  • Publication number: 20150119392
    Abstract: This invention provides compounds of Formula I: (Formula I should be inserted here) or a pharmaceutically acceptable salt thereof; pharmaceutical compositions comprising a compound of Formula I; and use of a compound of Formula I for treating specified cancers.
    Type: Application
    Filed: March 5, 2013
    Publication date: April 30, 2015
    Inventors: Daniel L. Flynn, Michael D. Kaufman, Lakshminarayana Vogeti, Scott Wise, Wei-Ping Lu, Bryan Smith, James R. Henry, Philip A. Hipskind, Sheng-Bin Peng
  • Publication number: 20150105367
    Abstract: This invention provides compounds of Formula (I) or a pharmaceutically acceptable salt thereof; pharmaceutical compositions comprising a compound of Formula (I); and use of a compound of Formula (I) for treating specified cancers.
    Type: Application
    Filed: March 5, 2013
    Publication date: April 16, 2015
    Inventors: Daniel L. Flynn, Michael D, Kaufman, Lakshminarayana Vogeti, Scott Wise, Wei-Ping Lu, Bryan Smith, Timothy Malcolm Caldwell, William C. Patt, James R. Henry, Philip A. Hipskind, Sheng-Bin Peng
  • Patent number: 7242234
    Abstract: An edge-triggered flip-flop is provided that includes one or more storage nodes and a pre-charge circuit in communication with the storage circuit. The storage circuit is configured to pre-charge the one or more storage nodes to a pre-determined voltage potential. The storage circuit further includes a first pull-down logic circuit in communication with the storage circuit and separate second pull-down logic circuit in communication with the storage circuit. The first pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to first input data and the second pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to second input data.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 10, 2007
    Assignee: Marvell International Ltd.
    Inventor: Wei-Ping Lu
  • Patent number: 6591286
    Abstract: An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: July 8, 2003
    Assignee: NeoMagic Corp.
    Inventor: Wei-Ping Lu
  • Patent number: 6549442
    Abstract: An associative processor uses a content-addressable memory (CAM) array to operate on data. The array has several CAM banks that store data in CAM memory cells. Each CAM bank has a register file that stores compare data that drives compare bit lines to the CAM cells, which activate row-match signals for rows with matching data. Each CAM bank has a register file with copies of compare data for all CAM banks. An index value identifies which of the compare registers drives the bank's compare bit lines. When a bank-swap instruction is executed, the index values of two banks are swapped, causing the compare data to be used for a different CAM bank. The physical data in the CAM banks is not swapped, but the compare data used for comparisons is swapped. Since the register files contain all banks' compare data, the compare data does not have to be physically moved.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: April 15, 2003
    Assignee: NeoMagic Corp.
    Inventors: Wei-Ping Lu, Yaron Serfaty, Fathy Yassa
  • Patent number: 6388471
    Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: May 14, 2002
    Assignee: SandCraft, Inc.
    Inventors: Wei-ping Lu, Tejvansh S. Soni, Victor Shadan, Edward Pak, Yuan-ping Chen
  • Patent number: RE39578
    Abstract: An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: April 17, 2007
    Assignee: Faust Communications, LLC
    Inventor: Wei-Ping Lu