Patents by Inventor Wei Qiang Jin

Wei Qiang Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit packaging system with interposer and method of manufacture thereof
    Patent number: 9184122
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer bottom side and an interposer top side; attaching a base integrated circuit to the interposer bottom side; attaching a lead to the interposer bottom side, the lead adjacent the base integrated circuit and entirely below the interposer; and forming an encapsulation partially covering the lead and exposing the interposer top side.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Wei Qiang Jin, Ding Hui Xu
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20130328216
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer bottom side and an interposer top side; attaching a base integrated circuit to the interposer bottom side; attaching a lead to the interposer bottom side, the lead adjacent the base integrated circuit and entirely below the interposer; and forming an encapsulation partially covering the lead and exposing the interposer top side.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Inventors: Wei Qiang Jin, Ding Hui Xu
  • INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110248391
    Abstract: A method of manufacture of an integrated circuit package stacking system includes: providing a bottom package including: providing a first lead frame, forming a bottom package body having the first lead frame in an off-centered parting line position, and forming bottom connection leads of the first lead frame for providing coplanar contacts at an end of the bottom connection leads; mounting a top package on the bottom package including: providing a second lead frame, forming a top package body on the second lead frame, and reforming top connection leads of the second lead frame for over-lapping contact areas on the bottom connection leads of the bottom package; and applying a conductive adhesive on the contact areas for electrically connecting the top connection leads and the bottom connection leads.
    Type: Application
    Filed: May 18, 2010
    Publication date: October 13, 2011
    Inventors: Wei Qiang Jin, Jae Hak Yee, Ya Ping Wang
  • Integrated circuit package system for chip on lead
    Patent number: 7701042
    Abstract: An integrated circuit package system includes providing an integrated circuit die having planar dimensions; forming a lead extended across one of the planar dimensions of the integrated circuit die; and applying an adhesive layer over the lead of a side opposite the integrated circuit die.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: April 20, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Shao Jian Chen, Wei Qiang Jin, Bhoy Ching, Taw Ming Lau