Abstract: A data input device includes a first delay line, a second delay line, a detection circuit, and a processing circuit. The detection circuit is configured to detect whether a first output data output to a system circuit deviates from a first detection range and to generate a first deviation signal in response to that the detection circuit detects the first output data deviates from the first detection range. The processing circuit normally takes a first delayed data delayed by the first delay line as the first output data. In response to that the processing circuit receives that the first deviation signal representing the first delayed data deviates from the first detection range, the processing circuit takes a second delayed data delayed by the second delay line as the first output data after the second adjustable delay magnitude of the second delay line is adjusted.

Abstract: A device for estimating breast implant volume is provided, which may include an input interface and a processing circuit. A numerical value may be inputted in to the input interface. The processing circuit may calculate the estimation value of breast implant volume according to a linear model and the numerical value. The processing circuit may multiply the numerical value by a coefficient to generate a product, and add a constant to the product to generate the estimation value of breast implant volume, wherein the numerical value may be a breast sample weight or a breast size.

Abstract: A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.

Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

Abstract: An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

Abstract: A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

Abstract: A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

Abstract: A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

Abstract: A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.