Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

Abstract: A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: A display device includes a first substrate, first signal lines, second signal lines, active elements, pixel electrodes, a second substrate, a black matrix, a first spacer, and a second spacer. The active elements are electrically connected with the first signal lines and the second signal lines. The black matrix includes first portions and second portions. The first portions overlap the first signal lines. The second portions overlap the second signal lines. The first spacer overlaps a source and a drain of one of the active elements. The second spacer overlaps a source and a drain of another one of the active elements. The shortest distance between the center of the first spacer and the center line of the closest one of the first portions is different from the shortest distance between the center of the second spacer and the center line of the closest one of the first portions.

Abstract: A display device includes a first substrate, first signal lines, second signal lines, active elements, pixel electrodes, a second substrate, a black matrix, a first spacer, and a second spacer. The active elements are electrically connected with the first signal lines and the second signal lines. The black matrix includes first portions and second portions. The first portions overlap the first signal lines. The second portions overlap the second signal lines. The first spacer overlaps a source and a drain of one of the active elements. The second spacer overlaps a source and a drain of another one of the active elements. The shortest distance between the center of the first spacer and the center line of the closest one of the first portions is different from the shortest distance between the center of the second spacer and the center line of the closest one of the first portions.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.

Abstract: A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

Abstract: A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.