Abstract: A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Abstract: A method of storage space management for a storage device comprising a controller and a memory, comprising: calculating, by the controller, an expectedly used capacity and an effective capacity of the memory, wherein the effective capacity has a negative correlation with a number of blocks marked as bad blocks among a plurality of blocks of the memory; when the effective capacity is less than or equal to the declared capacity, and a difference between the effective capacity and the expectedly used capacity is less than a predetermined threshold capacity, prohibiting, by the controller, programming to the memory; and when the effective capacity is less than or equal to the declared capacity and the difference of the effective capacity and the expectedly used capacity is not less than the predetermined threshold capacity, permitting, by the controller, programming to the memory.

Abstract: A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Abstract: A method of storage space management for a storage device comprising a controller and a memory, comprising: calculating, by the controller, an expectedly used capacity and an effective capacity of the memory, wherein the effective capacity has a negative correlation with a number of blocks marked as bad blocks among a plurality of blocks of the memory; when the effective capacity is less than or equal to the declared capacity, and a difference between the effective capacity and the expectedly used capacity is less than a predetermined threshold capacity, prohibiting, by the controller, programming to the memory; and when the effective capacity is less than or equal to the declared capacity and the difference of the effective capacity and the expectedly used capacity is not less than the predetermined threshold capacity, permitting, by the controller, programming to the memory.

Abstract: A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.

Abstract: The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

Abstract: A memory device includes a data calculation circuit, a space calculation circuit, and a warning circuit. The data calculation circuit is coupled to a memory, and is configured to determine a data quantity of valid data stored in the memory. The space calculation circuit is coupled to the memory, and is configured to determine a data capacity of a current valid storage space of the memory. The warning circuit is configured to determine a threshold capacity according to the data quantity, and is configured to determine whether to output a warning message according to the data capacity, the data quantity, and the threshold capacity.

Abstract: The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module is arranged to determine a first user behavior model or a second user behavior model to generate a determination result according to a plurality of access commands and/or a plurality of parameters of a memory module controlled by the memory module. When the determination result indicates the first user behavior model, the microprocessor uses a first control strategy to control the memory module; and when the determination result indicates the second user behavior model, the microprocessor uses a second control strategy different from the first control strategy to control the memory module.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.